74AUP1G374GW: 低功耗D型触发器;正沿触发器(三态)

74AUP1G374提供具有三态输出的单路D类触发器。该触发器会存储它们各自的数据输入(D)状态,满足从低到高CP转换的建立和保持时间要求。引脚OE为低电平时,触发器的内容在(Q)输出处可用。引脚OE为高电平时,输出会进入高阻抗关断状态。输入引脚OE的操作不会影响触发器的状态。

所有输入的施密特触发器动作使电路在0.8 V至3.6 V的整个VCC范围内容许较缓慢的输入上升时间和下降时间。该器件可确保在0.8 V至3.6 V的整个VCC范围内具有极低的静态和动态功耗。

该器件完全指定用于使用IOFF的部分掉电应用。IOFF电路可禁用输出,从而防止掉电时电流回流对器件造成的损坏。

74AUP1G374GW: 产品结构框图
74AUP1G374GW: 应用结构框图
74AUP1G374GW: 应用结构框图
SOT363
数据手册 (1)
名称/描述Modified Date
Low-power D-type flip-flop; positive-edge trigger; 3-state (REV 8.0) PDF (218.0 kB) 74AUP1G374 [English]29 Nov 2012
应用说明 (3)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
手册 (3)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic surface-mounted package; 6 leads (REV 1.0) PDF (246.0 kB) SOT363_1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (188.0 kB) SOT363_125 [English]20 Nov 2012
支持信息 (3)
名称/描述Modified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]30 Sep 2013
Wave Soldering Profile (REV 1.0) PDF (20.0 kB) WAVE_SOLDERING_PROFILE [English]30 Sep 2013
MAR_SOT363 Topmark (REV 1.0) PDF (104.0 kB) MAR_SOT363 [English]03 Jun 2013
IBIS
订购信息
型号状态FamilyVCC (V)功能Logic switching levels说明Output drive capability (mA)Package versiontpd (ns)fmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP1G374GWActiveAUP1.1 - 3.6D-type flip-flopsCMOSpositive-edge trigger (3-state)+/- 1.9SOT3637.9400ultra low-40~12526438.6153TSSOP66
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74AUP1G374GWSOT363Reflow_Soldering_Profile Wave_Soldering_Profile
Reflow_Soldering_Profile Wave_Soldering_Profile
Reel 7" Q3/T4, ReverseActive74AUP1G374GW,125 (9352 806 23125)aX74AUP1G374GWAlways Pb-free0.03.293.04E811
Low-power D-type flip-flop; positive-edge trigger; 3-state 74AUP1G374GW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT363 Topmark BSS84AKS
aup1g374 IBIS model 74AUP1G374GW
plastic surface-mounted package; 6 leads BSS84AKS
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
Tape reel SMD; reversed product orientation 12NC ending 125 74LVC2G17_Q100
74AUP1G374
74AVCM162836DGG
BFU520Y