74LVC157AD: Quad 2-input multiplexer

The 74LVC157A is a quad 2-input multiplexer which select four bits of data from two sources under the control of a common select input (S). The four outputs present the selected data in the true (non-inverted) form. The enable input (E) is active LOW. When pin E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74LVC157A. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator.

It is useful for implementing highly irregular logic by generating any 4 of the 16 different functions of two variables with one variable common.

The device is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to pin S.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.

74LVC157AD: Product Block Diagram
sot109-1_3d
Data Sheets (1)
Name/DescriptionModified Date
Quad 2-input multiplexer (REV 7.0) PDF (281.0 kB) 74LVC157A [English]25 Nov 2011
Application Notes (5)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]04 Feb 2011
Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English]05 Feb 2002
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]15 Sep 1995
Package Information (1)
Name/DescriptionModified Date
plastic small outline package; 16 leads; body width 3.9 mm (REV 1.0) PDF (192.0 kB) SOT109-1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
SO16; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... (REV 4.0) PDF (210.0 kB) SOT109-1_118 [English]24 Apr 2013
Supporting Information (2)
Name/DescriptionModified Date
Footprint for reflow soldering (REV 1.0) PDF (9.0 kB) SO-SOJ-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (8.0 kB) SO-SOJ-WAVE [English]08 Oct 2009
IBIS Model
SPICE model
Ordering Information
ProductStatusFamilyVCC (V)FunctionDescriptionLogic switching levelsPackage versionOutput drive capability (mA)tpd (ns)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVC157ADActiveLVC1.2 - 3.6Digital multiplexersquad 2-input multiplexerCMOS/LVTTLSOT109-1+/- 242.5low-40~1259310.353.3SO1616
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74LVC157ADSOT109-1SO-SOJ-REFLOW SO-SOJ-WAVE
SO-SOJ-REFLOW SO-SOJ-WAVE
Reel 13" Q1/T1Active74LVC157AD,118 (9352 608 98118)74LVC157AD74LVC157ADweek 35, 2004123.83.872.58E811
Bulk PackActive74LVC157AD,112 (9352 608 98112)74LVC157AD74LVC157ADweek 35, 2004123.83.872.58E811
Quad 2-input multiplexer 74LVC157APW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Pin FMEA for LVC family 74LVC1G123_Q100
Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
lvc157a IBIS model 74LVC157APW
lvc Spice model 74LVC3G17GT
plastic small outline package; 16 leads; body width 3.9 mm NPIC6C596A_Q100
Footprint for reflow soldering NPIC6C596A_Q100
Footprint for wave soldering NPIC6C596A_Q100
SO16; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... NPIC6C596A_Q100
74LVC157A
SA614A