74LVC16373ADL: 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.
The device consists of two sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are transparent, that is, the latch outputs change each time its corresponding D-input changes. The latches store the information that was present at the D-inputs one set-up time (tsu) preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.
74LVC16373ADL: Product Block Diagram
Outline 3d SOT370-1
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| 16-bit D-type transparant latch with 5 V tolerant inputs/outputs; 3-state (REV 8.0) PDF (207.0 kB) 74LVC_LVCH16373A [English] | 06 Jan 2014 |
Application Notes (6)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English] | 13 Mar 2013 |
| Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English] | 04 Feb 2011 |
| Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English] | 05 Feb 2002 |
| Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English] | 15 Sep 1995 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic shrink small outline package; 48 leads; body width 7.5 mm (REV 1.0) PDF (482.0 kB) SOT370-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Standard product orientation 12NC ending 118 (REV 2.0) PDF (87.0 kB) SOT370-1_118 [English] | 19 Apr 2013 |
Supporting Information (2)
| Name/Description | Modified Date |
|---|---|
| Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English] | 08 Oct 2009 |
| Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
IBIS Model
- lvc163 IBIS model (REV 1.0) ibs LVC163 4/7/2013
- lvc16373a IBIS model (REV 1.0) ibs LVC16373A 4/7/2013
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Package version | Output drive capability (mA) | tpd (ns) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC16373ADL | Active | LVC | 1.2 - 3.6 | Latches/registered drivers | TTL | 16-bit D-type transparent latch (3-state) | SOT370-1 | +/- 24 | 3 | 16 | low | -40~125 | 88 | 25.0 | SSOP48 | 48 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC16373ADL | | SOT370-1 | SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE | Reel 13" Q1/T1 | Active | 74LVC16373ADL,118 (9352 351 60118) | LVC16373A | 74LVC16373ADL |    | week 13, 2005 | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
| Bulk Pack | Active | 74LVC16373ADL,112 (9352 351 60112) | LVC16373A | 74LVC16373ADL | | week 13, 2005 | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- A metastability primer 74AHC573PW
- Pin FMEA for LVC family 74LVC1G123_Q100
- Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW
- Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- lvc163 IBIS model 74LVC163PW
- lvc16373a IBIS model 74LVC16373ADL
- plastic shrink small outline package; 48 leads; body width 7.5 mm gtl2000dl
- Footprint for reflow soldering 74HC_T_595_Q100
- SSOP-TSSOP-VSO-WAVE LPC1114FDH28
- Standard product orientation 12NC ending 118 gtl2000dl
- 74LVC_H_16373A
- 74LVT162245B
