MAC57D5xx: Ultra-Reliable Multi-Core ARM®-based MCU for Clusters and Display Management

The MAC57D5xx MCU family is a multi-core architecture solution for mid-range instrument cluster and industrial applications. This MCU is based on the ARM® Cortex®-M processor for real time and an ARM® Cortex®-A processors for applications and human machine interfaces that offer leading edge performance & scalability.

The MAC57D5xx MCU supports up to 2 WVGA resolution displays, one with in line head-up display hardware warping. The graphics content is generated using a powerful Vivante 2D GPU and the 2D animation and composition engine, to reduce memory footprint for content creation, integrated stepper motor drivers and a powerful I/O processor.

The MAC57D5xx MCU integrates NXP®.rsquo;s latest SHE-compliant CSE2 engine and delivers support ISO26262 ASIL-B functional safety compliance.

MAC57D5XX Block Diagram
MAC57D5x Instrument Cluster with HUD
特性
  • ARM®-based multi-core architecture platform
    • ARM® Cortex®-A5, 32-bit CPU (application processor)
    • ARM® Cortex®-M4, 32-bit CPU (vehicle processor)
    • ARM® Cortex®-M0+, 32-bit CPU (I/O processor)
  • ARM® Cortex®-A5, 32-bit CPU (application processor)
  • ARM® Cortex®-M4, 32-bit CPU (vehicle processor)
  • ARM® Cortex®-M0+, 32-bit CPU (I/O processor)
  • Intelligent stepper motor drive with stepper stall detect
  • Low-power mode peripheral management
  • Supports 2 x WVGA displays
  • On-the-fly Head Up Display (HUD) warping engine
  • Functional safety & security compliant
  • Ethernet 10/100 + AVB (ENET)
  • Autonomous real time clock (self calibrating)
  • QuadSPI Flash Controller utilizing the new Centered Read Strobe feature
  • Ultra-Reliable MCUs
Recommended Documentation (2)
Name/DescriptionTypeModified Date
MAC57D5xx - Fact Sheet (REV 3) PDF (250.2 kB) MAC57D5XXFSFact Sheets08 Aug 2016
QuadSPI Flash Controller utilizing the new Centered Read Strobe feature: An improved and simplified interface protocol... (REV 1) PDF (390.7 kB) CRSWPWhite Papers18 Mar 2015
Data Sheets (1)
Name/DescriptionModified Date
SAC57D54H Data Sheet (REV 5) PDF (1.3 MB) SAC57D54H17 May 2016
Application Notes (3)
Name/DescriptionModified Date
AN5285: MAC57D5xx Start-Up Sequence - Application notes (REV 0) PDF (324.5 kB) AN528502 May 2016
AN5265, MAC57D5xx Hardware Design Guidelines - Application note (REV 0) PDF (1.0 MB) AN526528 Apr 2016
AN5072, Introduction to Embedded Graphics with NXP® Devices-Application Notes (REV 0) PDF (796.7 kB) AN507209 Feb 2015
Reference Manuals (1)
Name/DescriptionModified Date
SAC57D54H Reference Manual (REV 4.2) PDF (19.9 MB) SAC57D54HRM18 May 2016
Users Guides (1)
Name/DescriptionModified Date
MAC57D5xxUG, MAC57D5xx Customer Evaluation Boards (REV 0) PDF (1.4 MB) MAC57D5XXUG04 May 2016
Engineering Bulletins (1)
Name/DescriptionModified Date
EB833: MAC57D5xx STCU BIST Configuration (REV 0) PDF (295.6 kB) EB83320 Mar 2016
Fact Sheets (1)
Name/DescriptionModified Date
MAC57D5xx - Fact Sheet (REV 3) PDF (250.2 kB) MAC57D5XXFS08 Aug 2016
White Papers (1)
Name/DescriptionModified Date
QuadSPI Flash Controller utilizing the new Centered Read Strobe feature: An improved and simplified interface protocol... (REV 1) PDF (390.7 kB) CRSWP18 Mar 2015
Ordering Information
ProductStatusStatusPackage Type and Termination CountCore TypeOperating Frequency (Max) (MHz)L1 CacheInternal RAM (KB)Internal Flash (KB)CANI2CSPILinFlex DMemory / Peripheral ProtectioneDMAExternal Memory SupportedVideo/Display featuresTimer/PWM
SAC57D54HCVMOActiveMAPBGA 516ARM Cortex-M4, ARM Cortex-M0+ IOP, ARM Cortex-A532032/32 on A5130040003253Yes2x 16ch32-Bit DDR2 DRAM (320mhz), 16-Bit SDR DRAM (160mhz), 2x Dual DDR QuadSPI2x 2D-ACE, HUD Warping Engine, Video Input Unit, Segment LCD, OpenVG 1.18ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer
SAC57D53MCVLTActiveLQFP 208ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M432032/32 on A5130030003253Yes2x 16ch2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz)OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer
SAC57D54HCVLTActiveLQFP 208ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M432032/32 on A5130040003253Yes2x 16ch2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz)OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer
SAC57D53MCVMOActiveMAPBGA 516ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M432032/32 on A5130030003253Yes2x 16ch2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz)OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer
SAC57D52LCVLTActiveLQFP 208ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M432032/32 on A5130020003253Yes2x 16ch2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz)OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer
Package Information
Package DescriptionOutline VersionPackingProduct StatusPart NumberChemical ContentRoHS / Pb FreeChina RoHS LookupMSLPPT (°C)
MAPBGA 516 27SQ*2.0 P1.098ASA00623DMPQ - 200 BRICKPOQ - 400 BOXActiveSAC57D54HCVMOSAC57D54HCVMO.pdf3260
MPQ - 200 BRICKPOQ - 400 BOXActiveSAC57D53MCVMOSAC57D53MCVMO.pdf3260
LQFPEP 208 28SQ P0.598ASA00649DMPQ - 180 BRICKPOQ - 360 BOXActiveSAC57D54HCVLTSAC57D54HCVLT.pdf3260
MPQ - 180 BRICKPOQ - 360 BOXActiveSAC57D53MCVLTSAC57D53MCVLT.pdf3260
MPQ - 180 BRICKPOQ - 360 BOXActiveSAC57D52LCVLTSAC57D52LCVLT.pdf3260