• 接收路径内置双通道10位模数转换器，支持内部或外部基准电压源接入，提供50 MSPS和80 MSPS两种型号
• 发射路径内置双通道10位、200 MSPS数模转换器，提供1x、2x或4x插值和可编程增益控制
• 内部时钟分配模块包括可编程锁相环(PLL)与时序产生电路，允许单一基准时钟操作
• 灵活的20位I/O数据接口，允许在半双工模式下进行各种交错或非交错数据传输，以及在全双工模式下进行交错数据传输
• 可通过SPI兼容端口或MODE选择引脚进行配置
• 独立的接收和发射关断控制引脚
• 64引脚、9 mm x 9 mm LFCSP封装
• 3个可配置辅助转换器引脚

• Receive Path Includes Dual 10-Bit Analog-To-Digital Converters with Internal or External Reference, 50 And 80 MSPS Versions
• Transmit Path Includes Dual 10-Bit, 200 MSPS Digital-to-Analog Converters with 1x, 2x, Or 4x Interpolation and Programmable Gain Control
• Internal Clock Distribution Block Includes a Programmable Phase-Locked-Loop and Timing Generation Circuitry Allowing Single Reference Clock Operation
• 20-Bit Flexible I/O Data Interface Allow Various Interleaved or Non-Interleaved Data Transfers in Half-Duplex Mode and Interleaved Data Transfers in Full-Duplex Mode
• Configurable through SPI Compliant Port or MODE Selection Pins
• Independent Rx and Tx Powerdown Control Pins
• 64 Lead lfCSP Package (9 mm x 9 mm Footprint)
• 3 Configurable Auxiliary Converter Pins

AD9861 技术指标

• Resolution (Bits): 10bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• ADC Architecture: Pipelined
• Pkg Type: CSP

AD9861 应用领域

• 宽带接入
• 宽带局域网（LAN）
• 通信（调制解调器）