CYPRESS赛普拉斯

CY2305/CY2309说明书.DOC

Low-cost 3.3V Zero Delay Buffer

Features

10-MHz to 100-/133-MHz operating range, compatible with CPU and PCI bus frequencies
Zero input-output propagation delay
60 ps typical cycle-to-cycle jitter (high drive)
Multiple low-skew outputs
- 85 ps typical output-to-output skew
- One input drives five outputs (CY2305)
- One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)
Compatible with Pentium(R)-based systems
Test Mode to bypass phase-locked loop (PLL) (CY2309 only [see "Select Input Decoding" on page 2])
Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil SOIC package (CY2305)
3.3V operation
Industrial temperature available

Functional Description

The CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions of each device operate at up to 100-/133-MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

The CY2309 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the "Select Input Decoding" table on page 2. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes.

The CY2305 and CY2309 PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 12.0 µA of current draw for commercial temperature devices and 25.0 µA for industrial temperature parts. The CY2309 PLL shuts down in one additional case.

Multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps.

The CY2305/CY2309 is available in two/three different configurations, as shown in the ordering information (page 10). The CY2305-1/CY2309-1 is the base part. The CY2305-1H/CY2309-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1s.

Part Number	Features	Frequency Range	Package	Status	Voltage (V)
CY2305/CY2309	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	8-Pin SOIC/16-Pin SOIC/16-Pin TSSOP	*Full Prodution	3.3
CY2305SC-1	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	8-Pin SOIC	Full Production	3.3
CY2305SC-1H	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	8-Pin SOIC	Full Production	3.3
CY2305SI-1	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	8-Pin SOIC	Full Production	3.3
CY2305SI-1H	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	8-Pin SOIC	Full Production	3.3
CY2305ZC-1H	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	8-Pin TSSOP	EOL	3.3
CY2309SC-1	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	16-Pin SOIC	Full Production	3.3
CY2309SC-1H	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	16-Pin SOIC	Full Production	3.3
CY2309SI-1	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	16-Pin SOIC	Full Production	3.3
CY2309SI-1H	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	16-Pin SOIC	Full Production	3.3
CY2309ZC-1H	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	16-Pin TSSOP	Full Production	3.3
CY2309ZI-1H	1 Ref. Input (LVCMOS & LVTTL), Internal feedback	133 MHz	16-Pin TSSOP	Full Production	3.3