IP1826A 24-port 10/100M + 2-port Gigabit Switch Controller
The IP 1826A is a non-blocking, store-and-forward architecture switch controller, which supports 24-port SS-SMII, and 2-port RGMII to constitutes a 26-port switch application. The 128-pin PQFP package makes it a very cost-effective solution for a 26-port switch.
Note: In the following paragraph, 24-port SS-SMII is referred to as port 0 ~ port 23 (or p0 ~ p23 for abbreviation). Gigabit port 1 and Gigabit port 2 is named as port 24(p24) and port 25(p25) respectively
The IP 1826A embeds a 2.75Mb SSRAM for the use of packet buffer and 4K MAC address table and also provides a 2-wire CPU interface, which allows designers to access to the internal registers of IP 1826A and the external PHY’s. The LED information is provided through a 2-wire LED interface by IP 1826A . With external logic devices, it can provide the status of link, speed, duplex and activity. The IP 1826A supports flow control, broadcast storm filtering, QoS (Quality of Service), port based VLAN, tag based VLAN, bi-direction per-port basis bandwidth control, port trunking, port mirroring and port security.
With the console management function, the designer can configure and monitor IP 1826A switch through hyper-terminal program built in Microsoft Windows without installing extra program
特性
- Provide 24 SS-SMII, 2-port RGMII and 2-wire CPU interface
- Built in 2.75Mb RAM
- Support packet length up to 1536 Bytes
- Store & forward, share memory, non-blocking architecture
- Support flow control
- 802.3x in full duplex
- Collision/carrier_sense based backpressure in half duplex
- Provide up to 4K MAC address entries
- CRC/ direct hashing algorithm
- Programmable aging timer (55s~15.7hr) < 4 % - Wire speed address learning and resolution - Learning enable/disable
- Support Port Mirroring function (in, out, in&out)
- Support flexible 2 trunking groups
- Port 0~Port 3 and Port 4~Port 7
- Load balance based on (port, DA, SA, DA/SA) - Link failure recovery
- Support VLAN
- Port based VLAN
- Tag based VLAN - Add/ remove/ modify tag
- Support Class of Service - Port based CoS
- 802.1Q priority tag based
- IP TOS based (IPv4/IPv6)
- 2 level per port
- WRR/ FIFS/ SP algorithm
- Broadcast storm control support - Broadcast rate control per chip
- Support port security- MAC address based
- IP address based
- Supports Bandwidth control- 479 configurable levels for P0~P25 (from 32kbps to 63.75 Mbps)
- With/without flow control
- PHY operating mode- Polling for speed, duplex, flow control, and link
- CPU can access to PHY register through IP 1826A
- Switch Configuration - Pin initial setting
- 2 wire serial interface for EEPROM
- 2 wire serial interface for CPU
- Counters for each port
- RX/TX packet count
- CRC error packet count - Drop packet count - Collision count
- Support serial driving LED functions
- Only one 25MHz crystal is needed
- Adjustable IO voltage (3.3/1.9V SS-SMII)
- Built in 2.5V and 1.9V regulator
- 128 pin PQFP lead-free package
- Programmable MAC address table through CPU interface
IP1826A 网络芯片图
