The 8XC196MC has a three phase waveform generator specifically designed for use in ‘‘Inverter’’ motorcontrol applications. This peripheral allows for pulse width modulation, three phase sine wave generation with minimal CPU intervention. It generates 3 complementary non-overlapping PWM pulses withThe 8XC196MC has 16 Kbytes on-chip OTPROM/ROM and 488 bytes of on-chip RAM. It is available in threepackages; PLCC (84-L), SDIP (64-L) and EIAJ/QFP (80-L). Note that the 64-L SDIP package does not include P1.4, P2.7, P5.1 and the CLKOUT pins. The 87C196MC contains 16 Kbytes on-chip OTPROM. The 83C196MC contains 16 Kbytes on-chip ROM. All
references to the 80C196MC also refers to the 83C196MC and 87C196MC unless noted.
| Symbol |
Function |
| ACH0 – ACH12 (P0.0 – P0.7, P1.0 – P1.4) |
Analog inputs to the on-chip A/D converter. ACH0 – 7 share the input pins with P0.0 – 7 and ACH8 – 12 share pins with P1.0 – 4. If the A/D is not used, the port pins can be used as standard input ports. |
| ANGND |
Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. |
| ALE/ADV(P5.0) |
Address Latch Enable or Address Valid output, as selected by CCR. Both options allow a latch to demultiplex the address/data bus on the signal’s falling edge. When the pin is ADV, it goes inactive (high) at the end of the bus cycle. ALE/ADV is active only during external memory accesses. Can be used as standard I/O when not used as ALE/ADV. |
| BHE/WRH (P5.5) |
Byte High Enable or Write High output, as selected by the CCR. BHE will go low for external writes to the high byte of the data bus. WRH will go low for external writes where an odd byte is being written. BHE/WRH is activated only during external memory writes. |
| BUSWIDTH (P5.7) |
Input for bus width selection. If CCR bits 1 and 2 e 1, this pin dynamically controls the bus width of the bus cycle in progress. If BUSWIDTH is low, an 8-bit cycle occurs. If it is high, a 16-bit cycle occurs. This pin can be used as standard I/O when not used as BUSWIDTH. |
| CAPCOMP0 – CAPCOMP3 (P2.0 – P2.3) |
The EPA Capture/Compare pins. These pins share P2.0 – P2.3. If not used for the EPA, they can be configured as standard I/O pins. |
| CLKOUT |
Output of the internal clock generator. The frequency is (/2 of the oscillator frequency. It has a 50% duty cycle. |
| COMPARE0 – COMPARE3 (P2.4 – P2.7) |
The EPA Compare pins. These pins share P2.4 – P2.7. If not used for the EPA, they can be configured as standard I/O pins. |
| EA |
External Access enable pin. E A e 0 causes all memory accesses to be external to the chip. EA e 1 causes memory accesses from location 2000H to 5FFFH to be from the on-chip OTPROM/QROM. EA e 12.5V causes execution to begin in the programming mode. EA is latched at reset. |
| EXTINT |
A programmable input on this pin causes a maskable interrupt vector through memory location 203CH. The input may be selected to be a positive/negative edge or a high/low level using WGPROTECT (1FCEH). |
| INST (P5.1) |
INST is high during the instruction fetch from the external memory and throughout the bus cycle. It is low otherwise. This pin can be configured as standard I/O if not used as INST. |
| NMI |
A positive transition on this pin causes a non-maskable interrupt which vectors to memory location 203EH. If not used, it should be tied to VSS. May be used by Intel Evaluation boards. |
| PORT0 |
8-bit high impedance input-only port. Also used as A/D converter inputs. Port0 pins should not be left floating. These pins also used to select programming modes in the OTPROM devices. |
| PORT1 |
5-bit high impedance input-only port. P1.0 – P1.4 are also used as A/D converter inputs. In addition, P1.2 and P1.3 can be used as Timer 1 clock input and direction select respectively. |
| PORT2 |
8-bit bidirectional I/O port. All of the Port2 pins are shared with the EPA I/O pins (CAPCOMP0 – 3 and COMPARE0 – 3). |
| PORT3 PORT4 |
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which uses strong internal pullups. |
| PORT5 |
8-bit bidirectional I/O port. 7 of the pins are shared with bus control signals (ALE, INST, WR, RD, BHE, READY, BUSWIDTH). Can be used as standard I/O. |
| PORT6 |
8-bit output port. P6.6 and P6.7 output PWM, the others are used as the Wave Form Generator outputs. Can be used as standard output ports. |
| PWM0, PWM1 (P6.6, P6.7) |
Programmable duty cycle, Programmable frequency Pulse Width Modulator pins. The duty cycle has a resolution of 256 steps, and the frequency can vary from 122 Hz to 31 KHz (16 MHz input clock). Pins may be configured as standard output if PWM is not used. |
| RD (P5.3) |
Read signal output to external memory. RD is low only during external memory reads. Can be used as standard I/O when not used as RD. |
| READY (P5.6) |
Ready input to lengthen external memory cycles. If READY e 0, the memory controller inserts wait states until the next positive transition of CLKOUT occurs with READY e 1. Can be used as standard I/O when not used as READY. |
| RESET |
Reset input to and open-drain output from the chip. Held low for at least 16 state times to reset the chip. Input high for normal operation. RESET has an Ohmic internal pullup resistor. |
| T1CLK (P1.2) |
Timer 0 Clock input. This pin has two other alternate functions: ACH10 and P1.2. |
| T1DIR (P1.3) |
Timer 0 Direction input. This pin has two other alternate functions: ACH11 and P1.3. |
| VPP |
The programming voltage is applied to this pin. It is also the timing pin for the return from Power Down circuit. Connect this pin with a 1 mF capacitor to VSS anda1 MX resistor to VCC. If the Power Down feature is not used, connect the pin to VCC. |
| WG1 – WG3/WG1 – WG3 (P6.0 – P6.5) |
3 phase output signals and their complements used in motor control applications. The pins can also be configured as standard output pins. |
| WR/WRL (P5.2) |
Write and Write Low output to external memory. WR will go low every external write. WRL will go low only for external writes to an even byte. Can be used as standard I/O when not used as WR/WRL. |
| XTAL1 |
Input of the oscillator inverter and the internal clock generator. This pin should be used when using an external clock source. |
| XTAL2 |
Output of the oscillator inverter. |
| PMODE (P0.4 – 7) |
Determines the EPROM programming mode. |
| PACT (P2.5) |
A low signal in Auto Programming mode indicates that programming is in process. A high signal indicates programming is complete. |
| PALE (P2.1) |
A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that ports 3 and 4 contain valid programming address/command information (input to slave). |
| PROG (P2.2) |
A falling edge in Slave Programming Mode begins programming. A rising edge ends programming. |
| PVER (P2.0) |
A high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly. |
| CPVER (P2.6) |
Cumulative Program Verification. Pin is high if all locations since entering a programming mode have programmed correctly. |
| AINC (P2.4) |
Auto Increment. Active low input enables the auto increment mode. Auto increment will allow reading or writing of sequential EPROM locations without address transactions across the PBUS for each read or write. |
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