MC100E310:2:8 Differential Clock/Data Fanout Buffer
The MC100E310 is a 2:8 Differential Clock/Data Fanout Buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part-to-part skew down to an output-to-output skew. This capability reduces the skew by a factor of 4 as compared to using two
LVE111's to accomplish the same task.
特性
- Dual Differential Fanout Buffers
- 200 ps Part-to-Part Skew
- 50 ps Typical Output-to-Output Skew
- Low Voltage ECL/PECL Compatible
- The 100 Series Contains Temperature Compensation
- 28-lead PLCC Packaging
- PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = ?4.2 V to ?5.7 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
- Internal Input Pulldown Resistors
- Q Output will Default LOW with Inputs Open or at VEE
- ESD Protection: >2KV HBM, >200V MM
- Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
- Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
- Flammability Rating: UL-94 code V-0 @ 1/8?, Oxygen Index 28 to 34
- Transistor Count = 179 devices
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封装图 PACKAGE DIMENSIONS
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC100E310FNG |
Active |
|
2:8 Differential Clock/Data Fanout Buffer |
PLCC-28 |
776-02 |
3 |
Tube |
37 |
|
| MC100E310FNR2G |
Active |
|
2:8 Differential Clock/Data Fanout Buffer |
PLCC-28 |
776-02 |
3 |
Tape and Reel |
500 |
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