MC100EL35:ECL JK Flip-Flop

The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.

技术特性
  • 525ps Propagation Delay
  • 2.2GHz Toggle Frequency
  • ESD Protection: > 1 kV HBM, > 100 V MM
  • PECL Mode Operating Range: VCC= 4.2 V to 5.7 with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors on J, K, CLK, and R
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1
    For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 V-0 @ 0.125 in, Oxygen Index: 28 to 34
  • Transistor Count = 81 devices
  • Pb-Free Packages are Available
封装图 MARKING DIAGRAM

MC100EL35 封装图

订购信息 Ordering Information
产品 状况 Compliance 具体说明 封装 MSL* 容器 预算价格 (1千个数量的单价)
类型 外形 类型 数量
MC100EL35DG Active
Pb-free
Halide free
ECL JK Flip-Flop SOIC-8 751-07 1 Tube 98  
MC100EL35DR2G Active
Pb-free
Halide free
ECL JK Flip-Flop SOIC-8 751-07 1 Tape and Reel 2500  
MC100EL35DTG Active
Pb-free
Halide free
ECL JK Flip-Flop TSSOP-8 948R-02 3 Tube 100  
MC100EL35DTR2G Active
Pb-free
Halide free
ECL JK Flip-Flop TSSOP-8 948R-02 3 Tape and Reel 2500  
MC100EL35MNR4G Active
Pb-free
Halide free
ECL JK Flip-Flop DFN-8 506AA 1 Tape and Reel 1000
数据资料DataSheet下载
概述 文档编号/大小 版本
ECL JK Flip-Flop MC100EL35-D(417.0kB) 1