MC100EP195:3.3 V ECL Programmable Delay Chip
NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers as shown in the data sheet logic diagram. The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D(0:9) which are latched on chip by a high signal on the latch enable (LEN) control. The MC10/100EP195 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in the data sheet.
技术特性
- Maximum Frequency > 1.2 Ghz Typical
- Programmable Range: 2.2 ns to 12.2 ns
- 10 ps Increments
- PECL Mode Operating Range: VCC = 3.0 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V
- Open Input Default State
- Safety Clamp on Inputs
- A Logic High on the ENbar Pin Will Force Q to Logic Low
- D[0:10] Can Accept Either ECL, CMOS, or TTL Inputs.
- VBB Output Reference Voltage
- Pb-Free Packages are Available
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封装图 MARKING DIAGRAM
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC100EP195FAG |
Active |
|
3.3 V ECL Programmable Delay Chip |
LQFP-32 |
873A-02 |
2 |
Tray JEDEC |
250 |
|
| MC100EP195FAR2G |
Active |
|
3.3 V ECL Programmable Delay Chip |
LQFP-32 |
873A-02 |
2 |
Tape and Reel |
2000 |
|
| MC100EP195MNG |
Active |
|
3.3 V ECL Programmable Delay Chip |
QFN-32 |
488AM |
1 |
Tube |
74 |
|
| MC100EP195MNR4G |
Active |
|
3.3 V ECL Programmable Delay Chip |
QFN-32 |
488AM |
1 |
Tape and Reel |
1000 |
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数据资料DataSheet下载
