MC100EP195B:3.3 V ECL Programmable Delay Chip
The MC100EP195B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP195B has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D(9:0) values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of real time delay values by D(9:0). A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D(10:0). The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 6 and Figure 3.
技术特性
- Maximum Input Clock Frequency >1.2 GHz Typical
- Programmable Range: 0 ns to 10 ns
- Delay Range: 2.2 ns to 12.2 ns
- 10 ps Increments
- PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V
- NECL Mode Operating Range:VCC = 0 V with VEE = 3.0 V to 3.6 V
- IN/INb Inputs Accept LVPECL, LVNECL, LVDS Levels
- A Logic High on the EN Pin Will Force Q to Logic Low
- D10:0 Can Select Either LVPECL, LVCMOS, or LVTTL Input Levels
- VBB Output Reference Voltage
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封装图 MARKING DIAGRAM
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC100EP195BFAG |
Active |
|
3.3 V ECL Programmable Delay Chip |
LQFP-32 |
873A-02 |
2 |
Tray JEDEC |
250 |
|
| MC100EP195BFAR2G |
Active |
|
3.3 V ECL Programmable Delay Chip |
LQFP-32 |
873A-02 |
2 |
Tape and Reel |
2000 |
|
| MC100EP195BMNG |
Active |
|
3.3 V ECL Programmable Delay Chip |
QFN-32 |
488AM |
1 |
Tube |
74 |
|
| MC100EP195BMNR4G |
Active |
|
3.3 V ECL Programmable Delay Chip |
QFN-32 |
488AM |
1 |
Tape and Reel |
1000 |
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数据资料DataSheet下载
