MC100EP35:ECL JK Flip-Flop

The MC10EP35 is a higher speed/low voltage version of the EL35JK flip flop. The J/K data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.

技术特性
  • 410 ps Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operatio Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0V to -5.5V
  • Open Input Default State
  • Q Output will default LOW with inputs open or at VEE
  • Pb-Free Packages are Available
封装图 MARKING DIAGRAM

MC100EP35 封装图

订购信息 Ordering Information
产品 状况 Compliance 具体说明 封装 MSL* 容器 预算价格 (1千个数量的单价)
类型 外形 类型 数量
MC100EP35DG Active
Pb-free
Halide free
ECL JK Flip-Flop SOIC-8 751-07 1 Tube 98  
MC100EP35DR2G Active
Pb-free
Halide free
ECL JK Flip-Flop SOIC-8 751-07 1 Tape and Reel 2500  
MC100EP35DTG Active
Pb-free
Halide free
ECL JK Flip-Flop TSSOP-8 948R-02 3 Tube 100  
MC100EP35DTR2G Active
Pb-free
Halide free
ECL JK Flip-Flop TSSOP-8 948R-02 3 Tape and Reel 2500  
MC100EP35MNR4G Active
Pb-free
Halide free
ECL JK Flip-Flop DFN-8 506AA 1 Tape and Reel 1000  
数据资料DataSheet下载
概述 文档编号/大小 版本
ECL JK Flip-Flop MC100EP35-D(417.0kB) 1