MC100EP51:ECL D Flip-Flop with Reset and Differential Clock
The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.
技术特性
- 350ps Typical Propagation Delay
- Maximum Frequency > 3 Ghz Typical
- PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
- Open Input Default State
- Safety Clamp on Inputs
- Pb-Free Packages are Available
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封装图 MARKING DIAGRAM
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC100EP51DG |
Active |
|
ECL D Flip-Flop with Reset and Differential Clock |
SOIC-8 |
751-07 |
1 |
Tube |
98 |
|
| MC100EP51DR2G |
Active |
|
ECL D Flip-Flop with Reset and Differential Clock |
SOIC-8 |
751-07 |
1 |
Tape and Reel |
2500 |
|
| MC100EP51DTG |
Active |
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ECL D Flip-Flop with Reset and Differential Clock |
TSSOP-8 |
948R-02 |
3 |
Tube |
100 |
|
| MC100EP51DTR2G |
Active |
|
ECL D Flip-Flop with Reset and Differential Clock |
TSSOP-8 |
948R-02 |
3 |
Tape and Reel |
2500 |
|
| MC100EP51MNR4G |
Active |
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ECL D Flip-Flop with Reset and Differential Clock |
DFN-8 |
506AA |
1 |
Tape and Reel |
1000 |
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数据资料DataSheet下载
