MC100EP52: ECL Differential Clock/Data D Flip-Flop

The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to VEE ) the outputs of the device will remain stable.

技术特性
  • 330ps Typical Propagation Delay
  • Maximum Frequency > 4 GHz Typical
  • PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output will default LOW with inputs open or at VEE
  • Pb-Free Packages are Available
封装图 MARKING DIAGRAM

MC100EP52 封装图

订购信息 Ordering Information
产品 状况 Compliance 具体说明 封装 MSL* 容器 预算价格 (1千个数量的单价)
类型 外形 类型 数量
MC100EP52DG Active
Pb-free
Halide free
ECL Differential Clock/Data D Flip-Flop SOIC-8 751-07 1 Tube 98  
MC100EP52DR2G Active
Pb-free
Halide free
ECL Differential Clock/Data D Flip-Flop SOIC-8 751-07 1 Tape and Reel 2500  
MC100EP52DTG Active
Pb-free
Halide free
ECL Differential Clock/Data D Flip-Flop TSSOP-8 948R-02 3 Tube 100  
MC100EP52DTR2G Active
Pb-free
Halide free
ECL Differential Clock/Data D Flip-Flop TSSOP-8 948R-02 3 Tape and Reel 2500  
MC100EP52MNR4G Active
Pb-free
Halide free
ECL Differential Clock/Data D Flip-Flop DFN-8 506AA 1 Tape and Reel 1000  
数据资料DataSheet下载
概述 文档编号/大小 版本
ECL Differential Clock/Data D Flip-Flop MC100EP52-D(417.0kB) 1