MC100LVE210:ECL Dual 1:4, 1:5 Differential Clock/Data Fanout Buffer-BDTIC代理MC100LVE210

MC100LVE210:ECL Dual 1:4, 1:5 Differential Clock/Data Fanout Buffer

The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part-to-part skew down to an output-to-output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111's to accomplish the same task.

特性

200ps Part-to-Part Skew.
50ps Output-to-Output Skew
ESD Protection: >2 KV HBM, >200 V MM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 250 devices
Pb-Free Packages are Available

封装图 PACKAGE DIMENSIONS

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具体说明

封装

MSL*

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类型

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类型

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MC100LVE210FNG

Active

Pb-free

Halide free

ECL Dual 1:4, 1:5 Differential Clock/Data Fanout Buffer

PLCC-28

776-02

Tube

MC100LVE210FNR2G