MC100LVE222:3.3 V ECL 1:15 Differential ÷·1/÷·2 Clock Driver
The MC100LVE222 is a low skew 3.3 V supply 2:1:4 clock distribution fanout buffer. An input MUX selects either a Fundamental Parallel Mode Crystal or a LVCMOS/LVTTL Clock by using the CLK_SEL pin (HIGH for Crystal, LOW for Clock) with LVCMOS / LVTTL levels. The single ended CLK input is translated to four LVPECL Outputs. Using the crystal input, the MC100LVE222 can be a Clock Generator. A CLK_EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output).
特性
- Four Differential LVPECL Outputs
- Selectable Crystal or LVCMOS/LVTTL CLOCK Inputs
- Operating Range: VCC = 3.3 5% V( 3.135 to 3.465 V)
- PbFree TSSOP20 Package
- Up to 266 MHz Clock Operation
- Output to Output Skew: 30 ps (Typ)
- Device to Device Skew 200 ps (Max)
- Propagation Delay 1.8 ns (Max)
- Additive Phase Jitter, RMS: 0.053 ps (Typ.)
- Synchronous Clock Enable Control
- Industrial Temp. Range (40C to 85C)
- These are PbFree Devices
- 10Gigibit Ethernet
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封装图 PACKAGE DIMENSIONS
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC100LVE222DTG |
Active |
|
3.3 V ECL 1:15 Differential ÷·1/÷·2 Clock Driver |
TSSOP-20 |
948E-02 |
1 |
Tube |
75 |
|
| MC100LVE222DTR2G |
Active |
|
3.3 V ECL 1:15 Differential ÷·1/÷·2 Clock Driver |
TSSOP-20 |
948E-02 |
1 |
Tape and Reel |
2500 |
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数据资料DataSheet下载
