MC100LVEP111:2.5 V / 3.3 V 1:10 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer
The MC100LVEP111 is a low skew 1-to-9 differential bus clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are one differential HSTL and one differential LVPECL. Both input pairs can accept LVDS levels. They are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous so that the outputs will only be enabled/disabled when they are already in LOW state.
特性
- 100 ps Typical Device-to-Device Skew
- 15 ps Typical Within Device Skew
- HSTL Compatible Outputs Drive 50Ω to Ground with no Offset Voltage
- Maximum Frequency > 750 MHz
- 850 ps Typical Propagation Delay
- Fully Compatible with Micrel SY89809L
- PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V
- Open Input Default State
- Pb-Free Packages are Available
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封装图 PACKAGE DIMENSIONS
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC100LVEP111FAG |
Active |
|
2.5 V / 3.3 V 1:10 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer |
LQFP-32 |
873A-02 |
2 |
Tray JEDEC |
250 |
|
| MC100LVEP111FAR2G |
Active |
|
2.5 V / 3.3 V 1:10 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer |
LQFP-32 |
873A-02 |
2 |
Tape and Reel |
2000 |
|
| MC100LVEP111MNG |
Active |
|
2.5 V / 3.3 V 1:10 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer |
QFN-32 |
488AM |
1 |
Tube |
74 |
|
| MC100LVEP111MNR4G |
Active |
|
2.5 V / 3.3 V 1:10 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer |
QFN-32 |
488AM |
1 |
Tape and Reel |
1000 |
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