MC10E156:ECL 3-Bit 4:1 Mux-Latch

The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.

技术特性

950ps Max. D to Output
850ps Max. LEN to Output
Differential Outputs
Asynchronous Master Reset
Dual Latch-Enables
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
Internal Input Pulldown Resistors
ESD Protection: > 2 kV HBM, > 200 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 271 devices
Pb-Free Packages are Available

封装图 MARKING DIAGRAM

订购信息 Ordering Information

产品

状况

Compliance

具体说明

封装

MSL*

容器

预算价格 (1千个数量的单价）

类型

外形

类型

数量

MC10E156FNG

Active

Pb-free

Halide free

ECL 3-Bit 4:1 Mux-Latch

PLCC-28

776-02

Tube

MC10E156FNR2G