MC10EL34:5.0 V ECL ÷·2, ÷·4, ÷·8 Clock Generation Chip
The MC10/100EL34 is a low skew divide by 2, divide by 4, divide by 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPS Data Book DL140/D). If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 F capacitor. The VBB output is designed to act as the switching reference for the input of the EL34 under single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current.
技术特性
- 50ps Output-to-Output Skew
- Synchronous Enable/Disable
- Master Reset for Synchronization
- PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
- Pb-Free Packages are Available
- Internal Input Pulldown Resistors on CLK(s), ENbar, and MR
|
封装图 MARKING DIAGRAM
|
订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC10EL34DG |
Active |
|
5.0 V ECL ÷·2, ÷·4, ÷·8 Clock Generation Chip |
SOIC-16 |
751B-05 |
1 |
Tube |
48 |
|
| MC10EL34DR2G |
Active |
|
5.0 V ECL ÷·2, ÷·4, ÷·8 Clock Generation Chip |
SOIC-16 |
751B-05 |
1 |
Tape and Reel |
2500 |
|
数据资料DataSheet下载
