MC10EP139:3.3 V / 5.0 V ECL ÷·2/4, ÷·4/5/6 Divider
The MC10/100EP139 is a low skew divide by 2/4, divide by 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLKbar input and bypassed to ground via a 0.01uF capacitor.
技术特性
- Maximum Frequency >1.0 GHz Typical
- 50ps Output-to-Output Skew
- PECL Mode Operating Range: VCC=3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
- Open Input Default State
- Safety Clamp on Inputs
- Synchronous Enable/Disable
- Master Reset for Synchronization of Multiple Chips
- VBB Output
- Pb-Free Packages are Available
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封装图 MARKING DIAGRAM
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC10EP139DT |
Active, Not Rec  |
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3.3 V / 5.0 V ECL ÷·2/4, ÷·4/5/6 Divider |
TSSOP-20 |
948E-02 |
1 |
Tube |
75 |
|
| MC10EP139DTG |
Active |
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3.3 V / 5.0 V ECL ÷·2/4, ÷·4/5/6 Divider |
TSSOP-20 |
948E-02 |
1 |
Tube |
75 |
|
| MC10EP139DTR2 |
Active, Not Rec |
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3.3 V / 5.0 V ECL ÷·2/4, ÷·4/5/6 Divider |
TSSOP-20 |
948E-02 |
1 |
Tape and Reel |
2500 |
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| MC10EP139DTR2G |
Active |
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3.3 V / 5.0 V ECL ÷·2/4, ÷·4/5/6 Divider |
TSSOP-20 |
948E-02 |
1 |
Tape and Reel |
2500 |
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| MC10EP139DWG |
Active |
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3.3 V / 5.0 V ECL ÷·2/4, ÷·4/5/6 Divider |
SOIC-20W |
751D-05 |
3 |
Tube |
38 |
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| MC10EP139DWR2G |
Active |
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3.3 V / 5.0 V ECL ÷·2/4, ÷·4/5/6 Divider |
SOIC-20W |
751D-05 |
3 |
Tape and Reel |
1000 |
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