MC10EP51:3.3 V / 5.0 V ECL D Flip-Flop with Reset and Differential Clock
The MC10EP51 is a higher speed/low voltage version of the EL35JK flip flop. The J/K data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.
技术特性
- 410 ps Propagation Delay
- Maximum Frequency > 3 GHz Typical
- PECL Mode Operatio Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0V to -5.5V
- Open Input Default State
- Q Output will default LOW with inputs open or at VEE
- Pb-Free Packages are Available
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封装图 MARKING DIAGRAM
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC10EP51DG |
Active |
|
3.3 V / 5.0 V ECL D Flip-Flop with Reset and Differential Clock |
SOIC-8 |
751-07 |
1 |
Tube |
98 |
|
| MC10EP51DR2G |
Active |
|
3.3 V / 5.0 V ECL D Flip-Flop with Reset and Differential Clock |
SOIC-8 |
751-07 |
1 |
Tape and Reel |
2500 |
|
| MC10EP51DTG |
Active |
|
3.3 V / 5.0 V ECL D Flip-Flop with Reset and Differential Clock |
TSSOP-8 |
948R-02 |
3 |
Tube |
100 |
|
| MC10EP51DTR2G |
Active |
|
3.3 V / 5.0 V ECL D Flip-Flop with Reset and Differential Clock |
TSSOP-8 |
948R-02 |
3 |
Tape and Reel |
2500 |
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数据资料DataSheet下载
