MC14042B: Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic "0" state, data is transferred during the low clock level, and when the polarity input is in the logic "1" state the transfer occurs during the high clock level.
技术特性
- Buffered Data Inputs
- Common Clock
- Clock Polarity Control
- Q and Qbar Outputs
- Double Diode Input Protection
- Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
- Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
- Pb-Free Packages are Available*
|
封装图 MARKING DIAGRAM
|
订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC14042BCPG |
Lifetime |
|
Quad Transparent Latch |
PDIP-16 |
648-08 |
|
Tube |
500 |
$0.2933
|
| MC14042BDG |
Active |
|
Quad Transparent Latch |
SOIC-16 |
751B-05 |
1 |
Tube |
48 |
$0.28 |
| MC14042BDR2G |
Active |
|
Quad Transparent Latch |
SOIC-16 |
751B-05 |
1 |
Tape and Reel |
2500 |
$0.28 |
| NLV14042BDG |
Active |
| AEC Qualified |
| PPAP Capable |
| Pb-free |
| Halide free |
|
Quad Transparent Latch |
SOIC-16 |
751B-05 |
1 |
Tube |
48 |
$0.308 |
| NLV14042BDR2G |
Active |
| AEC Qualified |
| PPAP Capable |
| Pb-free |
| Halide free |
|
Quad Transparent Latch |
SOIC-16 |
751B-05 |
1 |
Tape and Reel |
2500 |
$0.308 |
数据资料DataSheet下载
