技术特性

• Available Outputs 28, 210, 213 or 216
• Increments on Positive Edge Clock Transitions
• Built-in Low Power RC Oscillator (+/- 2% accuracy over temperature range and +/- 20% supply and +/- 3% over processing at < 10 kHz)
• Oscillator May Be Bypassed if External Clock Is Available (Apply external clock to Pin 3)
• External Master Reset Totally Independent of Automatic Reset Operation
• Operates as 2n Frequency Divider or Single Transition Timer
• Q/Qbar Select Provides Output Logic Level Flexibility
• Reset (auto or master) Disables Oscillator During Resetting to Provide No Active Power Dissapation
• Clock Conditioning Circuit Permits Operation with Very Slow Clock Rise and Fall Times
• Automatic Reset Initializes All Counters On Power Up
• Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset Disabled (Pin 5 = VDD) 
  8.5 Vdc to 18 Vdc with Auto Reset Enabled (Pin 5 = VSS)
• Pb-Free Packages are Available*

封装图 MARKING DIAGRAM