NB100LVEP224:2.5 V / 3.3 V 1:24 Differential ECL/PECL Clock/Data Fanout Buffer with Clock Select and Output Enable
The NB100EP223 is a low skew 1-to-22 differential bus clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential HSTL or LVPECL and they are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous so that the outputs will only be enabled/disabled when they are already in LOW state (See Figure 7).
特性
- 100 ps Typical Device-to-Device Skew
- 25 ps Typical Within Device Skew
- HSTL Outputs Drive 50Ω to Ground With No Offset Voltage
- Maximum Frequency > 500 Mhz
- 1 ns Typical Propagation Delay
- LVPECL and HSTL Mode Operating Range: VCC = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V
- Q Output will Default Low with Inputs Open
- Thermally Enhanced 64-Lead LQFP
- CLOCK Inputs are LVDS-Compatible; Requires External 100 Ω LVDS Termination Resistor
- Pb-Free Packages are Available
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封装图 PACKAGE DIMENSIONS
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| NB100LVEP224FAG |
Active |
|
2.5 V / 3.3 V 1:24 Differential ECL/PECL Clock/Data Fanout Buffer with Clock Select and Output Enable |
QFP-64 / LQFP-64 |
848G |
3 |
Tray JEDEC |
160 |
|
| NB100LVEP224FARG |
Active |
|
2.5 V / 3.3 V 1:24 Differential ECL/PECL Clock/Data Fanout Buffer with Clock Select and Output Enable |
QFP-64 / LQFP-64 |
848G |
3 |
Tape and Reel |
1500 |
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