NB4L52:2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination

The NB4L52 is a differential Data and Clock D flip−flop with a differential asynchronous Reset. The differential inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3mm x 3mm 16 pin QFN package.

技术特性
  • Maximum Input Clock Frequency > 4 GHz Typical
  • 330 ps Typical Propagation Delay
  • 145 ps Typical Rise and Fall Times
  • Differential LVPECL Outputs, 750 mV PeaktoPeak, Typical
  • Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V
封装图 MARKING DIAGRAM

NB4L52 封装图

订购信息 Ordering Information
产品 状况 Compliance 具体说明 封装 MSL* 容器 预算价格 (1千个数量的单价)
类型 外形 类型 数量
NB4L52MNG Active
Pb-free
Halide free
2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination QFN-16 485G-01 1 Tube 123  
NB4L52MNR2G Active
Pb-free
Halide free
2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination QFN-16 485G-01 1 Tape and Reel 3000  
数据资料DataSheet下载
概述 文档编号/大小 版本
2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination NB4L52-D(417.0kB) 1