NB4N527S:Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 2.5 Gb/s or 1.25 GHz, respectively. The NB4N527S has a wide input common mode range of GND+50 mV to VCC-50 mV combined with two 50 Ω internal termination resistors is ideal for translating differential or single-ended data or clock signals to 350 mV typical LVDS output levels without use of any additional external components. The device is offered in a small 3 mm x 3 mm QFN-16 package. NB4N527S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements.
特性
- Maximum Input Clock Frequency up to 1.25 GHz
- Maximum Input Data Rate up to 2.5 Gb/s
- 500 ps Maximum Propagation Delay
- 2 ps Maximum RMS Jitter
- 300 ps Maximum Rise/Fall Times
- Single Power Supply; VCC = 3.3 V +/- 10%
- Temperature Compensated TIA/EIA644 Compliant LVDS Outputs
- Internal 50 Termination Resistor per Input Pin
- GND + 50 mV to VCC 50 mV VCMR Range
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封装图 PACKAGE DIMENSIONS
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| NB4N527SMNG |
Active |
|
Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination |
QFN-16 |
485G-01 |
1 |
Tube |
123 |
|
| NB4N527SMNR2G |
Active |
|
Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination |
QFN-16 |
485G-01 |
1 |
Tape and Reel |
3000 |
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