NB6L56:Clock / Data Multiplexer, 2.5 V / 3.3 V Dual 2:1 Differential, with LVPECL Outputs
The NB6L56 is a high performance Dual 2-to-1 Differential Clock or Data multiplexer. The Multi-Level differential inputs incorporate internal 50 Ohms termination resistors that are accessed through the VT pin. This feature allows the NB6L56 to accept various Differential logic level standards, such as LVPECL, CML or LVDS. Outputs are 800 mV LVPECL signals.
技术特性
- Maximum Input Data Rate > 2.5 Gbps
- Maximum Input Clock Frequency > 2.5 GHz
- Jitter is < 1 ps RMS RJ (Data); < 10 ps PP DJ (Data); and < 0.7 ps RMS Crosstalk induced jitter (CLOCK)
- 360 ps Max Propagation Delay
- 180 ps Max Rise and Fall Times
- Operating Range is VCC = 2.5 5% (2.375 V to 2.625 V with VEE = 0 V), or
VCC =3.3 10% (3.0 V to 3.6 V with VEE = 0 V)
- Internal 50 Input Termination Resistors
- Industrial Temp. Range (40C to 85C)
- QFN32 Package
|
封装图 MARKING DIAGRAM
|
订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| NB6L56MNG |
Active |
|
Clock / Data Multiplexer, 2.5 V / 3.3 V Dual 2:1 Differential, with LVPECL Outputs |
QFN-32 |
488AM |
1 |
Tube |
74 |
|
| NB6L56MNTXG |
Active |
|
Clock / Data Multiplexer, 2.5 V / 3.3 V Dual 2:1 Differential, with LVPECL Outputs |
QFN-32 |
488AM |
1 |
Tape and Reel |
1000 |
|
数据资料DataSheet下载
