NB6N14S: 3.3 V 1:4 AnyLevel™ Input to LVDS Fanout Buffer / Translator
The NB6N14S is a 3.3 V 1:4 AnyLevel™ Input to LVDS Fanout Buffer / Translator. The differential inputs incorporate internal 50-ohm termination resistors that are accessed through the VTD pins and will accept LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels. The VREFAC pin is an internally generated voltage supply available to this device only. VREFAC is used as a reference voltage for single-ended PECL or NECL inputs. For all single-ended input conditions, the unused complementary differential input is connected to VREFAC as a switching reference voltage. VREFAC may also rebias capacitor-coupled inputs. When used, decouple VREFAC with a 0.01uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VREFAC output should be left open. The device is housed in a small 3mm x 3mm 16-pin QFN package. The NB6N14S is a member of the ECLinPS MAX family of high performance clock and data management products.
特性
- Maximum Input Clock Frequency > 2.0 GHz
- Maximum Input Data Rate > 2.5 Gb/s
- 1 ps Maximum of RMS Clock Jitter
- Typically 10 ps of Data Dependent Jitter
- 380 ps Typical Propagation Delay
- 120 ps Typical Rise and Fall Times
- These devices are available in Pb-free package(s). Specifications herein
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封装图 PACKAGE DIMENSIONS
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| NB6N14SMNG |
Active |
|
3.3 V 1:4 AnyLevel™ Input to LVDS Fanout Buffer / Translator |
QFN-16 |
485G-01 |
1 |
Tube |
123 |
|
| NB6N14SMNR2G |
Active |
|
3.3 V 1:4 AnyLevel™ Input to LVDS Fanout Buffer / Translator |
QFN-16 |
485G-01 |
1 |
Tape and Reel |
3000 |
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