NB6N239S:3.3 V Any Differential Clock to LVDS,÷·1/2/4/8 and÷·2/4/8/16 Clock Divider
The NB6N239S is a high-speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; divide 1/2/4/8 and divide 2/4/8/16. Both divider circuits drive a pair of LVPECL outputs
技术特性
- Maximum Clock Input Frequency; ≥ 3GHz
- Input compatibility with LVDS/LVPECL/CML/HSTL
- 70 ps Typical Rise/Fall Times
- 5 ps Typcial Output-to-Output Skew
- Ex. 622.08MHz Input Generates 38.88MHz to 622.08 MHz Outputs
- Internal 50 Ω Termination Provided
- Random Clock Jitter ≤ 1 ps RMS
- Divide-by-1 Edge of QA Aligned to QB divided Output
- Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
- Master Reset for Synchronization of Multiple Chips
- VBBAC Reference Output
- Synchronous Output Disable/Enable
- Telecom/Datacom Routers, Swithes
- Pb-Free Packages are Available
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封装图 MARKING DIAGRAM
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| NB6N239SMNG |
Active |
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3.3 V Any Differential Clock to LVDS,÷·1/2/4/8 and÷·2/4/8/16 Clock Divider |
QFN-16 |
485G-01 |
1 |
Tube |
123 |
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| NB6N239SMNR2G |
Active |
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3.3 V Any Differential Clock to LVDS,÷·1/2/4/8 and÷·2/4/8/16 Clock Divider |
QFN-16 |
485G-01 |
1 |
Tape and Reel |
3000 |
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