NBSG16M:Multilevel Input to CML Clock/Data Receiver/ Driver/Translator Buffer
The NBSG16M is a differential current mode logic (CML) receiver/driver. The device is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities. Inputs incorporate internal 50 Ω termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The CML output structure contains internal 50 Ω source termination resistor to VCC. The device generates 400 mV output amplitude with 50 Ω receiver resistor to VCC. The VBB pin is internally generated voltage supply available to this device only. For all single−ended input conditions, the unused complementary differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open.
特性
- Maximum Input Clock Frequency > 10 GHz Typical
- Maximum Input Data Rate > 10 Gb/s Typical
- 120 ps Typical Propagation Delay
- 35 ps Typical Rise and Fall Times
- Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
- Negative CML Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
- CML Output Level; 400 mV Peak-to-Peak Output with 50 _ Receiver Resistor to VCC
- 50 Ω Internal Input and Output Termination Resistors
- Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL and SG Devices
- VBB Reference Voltage Output
- Pb-Free Packages are Available
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封装图 PACKAGE DIMENSIONS
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订购信息 Ordering Information
产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价) |
类型 |
外形 |
类型 |
数量 |
NBSG16MMNG |
Active |
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Multilevel Input to CML Clock/Data Receiver/ Driver/Translator Buffer |
QFN-16 |
485G-01 |
1 |
Tube |
123 |
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NBSG16MMNTXG |
Active |
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Multilevel Input to CML Clock/Data Receiver/ Driver/Translator Buffer |
QFN-16 |
485G-01 |
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Tape and Reel |
3000 |
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