SPC564A80L7 32-bit family built on the embedded Power Architecture®

The microcontroller’s e200z4 host processor core is built on Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).

技术特性

150 MHz e200z4 Power Architecture core
- Variable length instruction encoding (VLE)
- Superscalar architecture with 2 execution units
- Up to 2 integer or floating point instructions per cycle
- Up to 4 multiply and accumulate operations per cycle
Memory organization
- 4 MB on-chip flash memory with ECC and Read While Write (RWW)
- 192 KB on-chip RAM with standby functionality (32 KB) and ECC
- 8 KB instruction cache (with line locking), configurable as 2- or 4-way
- 14 + 3 KB eTPU code and data RAM
- 5 × 4 crossbar switch (XBAR)
- 24-entry MMU
- External Bus Interface (EBI) with slave and master port
Fail Safe Protection
- 16-entry Memory Protection Unit (MPU)
- CRC unit with 3 sub-modules
- Junction temperature sensor
Interrupts
- Configurable interrupt controller (with NMI)
- 64-channel DMA
Serial channels
- 3 × eSCI
- 3 × DSPI (2 of which support downstream Micro Second Channel [MSC])
- 3 × FlexCAN with 64 messages each
- 1 × FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC
1 × eMIOS
- 24 unified channels
1 × eTPU2 (second generation eTPU)
- 32 standard channels
- 1 × reaction module (6 channels with three outputs per channel)
2 enhanced queued analog-to-digital converters (eQADCs)
- Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers
- 6 command queues
- Trigger and DMA support
- 688 ns minimum conversion time
On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM)
Nexus: Class 3+ for core; Class 1 for the eTPU
JTAG (5-pin)
Development Trigger Semaphore (DTS)
Clock generation
- On-chip 4–40 MHz main oscillator
- On-chip FMPLL (frequency-modulated phase-locked loop)
Up to 120 general purpose I/O lines
- Individually programmable as input, output or special function
- Programmable threshold (hysteresis)
Power reduction mode: slow, stop and stand-by modes
Flexible supply scheme
- 5 V single supply with external ballast
- Multiple external supply: 5 V, 3.3 V and 1.2 V
Designed for LQFP176, LBGA208, PBGA324 and Known Good Die (KGD)

SPC564A80L7 订购信息

订购型号	产品状态	美金价格	数量	封装	包装形式	温度范围	材料声明
SPC564A80L7COBY	Proposal			LQFP 176 24x24x1.4	Tray	-40 °C-125 °C	SPC564A80L7COBY
SPC564A80L7CFBR	Active	20.58	1000	LQFP 176 24x24x1.4	Tape And Reel	-40 °C-125 °C	SPC564A80L7CFBR
SPC564A80L7CFCR	Active			LQFP 176 24x24x1.4	Tape And Reel	-40 °C-125 °C	SPC564A80L7CFCR
SPC564A74L7CFAR	Active	18.559	1000	LQFP 176 24x24x1.4	Tape And Reel	-40 °C-125 °C	SPC564A74L7CFAR
SPC564A74L7CFAY	Active	18.559	1000	LQFP 176 24x24x1.4	Tray	-40 °C-125 °C	SPC564A74L7CFAY
SPC564A80L7CFAR	Active	20.869	1000	LQFP 176 24x24x1.4	Tape And Reel	-40 °C-125 °C	SPC564A80L7CFAR
SPC564A80L7COBR	Proposal			LQFP 176 24x24x1.4	Tape And Reel	-40 °C-125 °C	SPC564A80L7COBR
SPC564A80L7CFBY	Active	20.58	1000	LQFP 176 24x24x1.4	Tray	-40 °C-125 °C	SPC564A80L7CFBY
SPC564A80L7CFCY	Active			LQFP 176 24x24x1.4	Tray	-40 °C-125 °C	SPC564A80L7CFCY
SPC564A74L7COBR	Proposal			LQFP 176 24x24x1.4	Tape And Reel	-40 °C-125 °C	SPC564A74L7COBR
SPC564A74L7COBY	Proposal			LQFP 176 24x24x1.4	Tray		SPC564A74L7COBY
SPC564A80L7CFAY	Active	20.869	1000	LQFP 176 24x24x1.4	Tray	-40 °C-105 °C	SPC564A80L7CFAY

DATASHEET

描述	版本	大小
DS6103: 32-bit MCU family built on the embedded Power Architecture®	8	1408KB

APPLICATION NOTES

描述	版本	大小
AN3995: Getting started tutorial for SPC564Bxx and SPC56ECxx family	1	442KB

ERRATA SHEETS

描述	版本	大小
ES0145: SPC564A80x device errata JTAG_ID = 0x1AE02041	4	155KB

REFERENCE MANUALS

描述	版本	大小
RM0029: SPC564A80B4, SPC564A80L7 32-bit MCU family built on the embedded Power Architecture®	2	14403KB

MARKETING BROCHURES

描述	版本	大小
BRSPC56M0212 : SPC563M, SPC564A	1.0.0	222KB