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ST10R272LT6 16位微控制器TQFP-100封装

16-bit low voltage ROMless MCU with MAC

ST10R272LT6 概述

ST10R272L architecture combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem. The following block diagram overviews the different onchip components and the internal bus structure.

The main core of the CPU contains a 4-stage instruction pipeline, a MAC multiplyaccumulation unit, a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most instructions can be executed in one machine cycle requiring 40ns at 50MHz CPU clock.

The CPU includes an actual register context consisting of 16 wordwide GPRs physically located in the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, one register bank may overlap others.

A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are compared against the stack pointer value during each stack access to detect stack overflow or underflow.

ST10R272LT6 特性:

• High Performance 16-bit CPU
  CPU Frequency: 0 to 50 MHz
  40ns instruction cycle time at 50-MHz CPU
  clock
  Multiply-Accumulate unit (MAC)
  4-stage pipeline
  Register-based design with multiple
  variable register banks
  Enhanced boolean bit manipulation
  facilities
  Additional instructions to support HLL and
  operating systems
  Single-cycle context switching support
  1024 bytes on-Chip special function
  register area
• Memory Organisation
  1KByte on-chip RAM
  Up to 16 MBytes linear address space for
  code and data (1 MByte with SSP used)
• External Memory Interface
  Programmable external bus characteristics
  for different address ranges
  8-bit or 16-bit external data bus
  Multiplexed or demultiplexed external
  address/data buses
  Five programmable chip-select signals
  Hold and hold-acknowledge bus arbitration
  support
• One Channel PWM Unit
  Fail Safe Protection
  Programmable watchdog timer
  Oscillator Watchdog
• Interrupt
  8-channel interrupt-driven single-cycle data
  transfer facilities via peripheral event
  controller (PEC)
  16-priority-level interrupt system with 17
  sources, sample-rate down to 40 ns
• Timers
  Two multi-functional general purpose timer
  units with 5 timers
  Clock Generation via on-chip PLL, or via
  direct or prescaled clock input
• Serial Channels
  Synchronous/asynchronous
  High-speed-synchronous serial port SSP
• Up to 77 general purpose I/O lines
• No bootstrap loader
• Electrical Characteristics
  5V Tolerant I/Os
  5V Fail-Safe Inputs (Port 5)
  Power: 3.3 Volt +/-0.3V
  Idle and power down modes
• Support
  C-compilers, macro-assembler packages,
  emulators, evaluation boards, HLLdebuggers,
  simulators, logic analyser
  disassemblers, programming boards
• Package
  100-Pin Thin Quad Flat Pack (TQFP)

ST10R272LT6 订购型号:

1. ST10R272LT1
2. ST10R272LT6

ST10R272LT6 技术支持与电子电路设计开发资源下载

1. ST10R272L 数据手册 DataSheet 下载.pdf
2. ST10 16位微控制器选型参数
3. 手册和产品指南.pdf
4. 8、16、32位微控制器.pdf
5. 意法半导体应用支持 . PDF
6. 先进半导体解决方案的门电子
7. 电机控制参考指南
8. 周围半导体机顶盒应用. PDF
9. STM32,STR7和STR9开发工具 . PDF
10. 8 ,16和32位微控制器产品和工具选择指南. PDF
11. 电机控制选型指南. PDF