技术特性

• 2 Satellite and 1 terrestrial signal demodulators and decoders
• Advanced DSP processor to implement PAC audio decoder
• Requires a single 17MHz clock reference; all high-speed clock signals are derived using on-chip PLL
• Programmable I2S to support 32K/48K/44.1K audio sample rate (32K/48K Sample rates use internal clocks, 44.1K Sample rate uses external clock)
• I²C master interface to control tuner and audio DAC
• External control through UART interface using Sirius Standard Protocol (SSP) over RS-232
  • Analog to digital converters
  • Three internal 10 BIT A/D converters for 76.5MHZ if signals conversion
• Low power technology
  • 1.2V, 90 μm technology
  • 2.5V capable I/OS

功能框图