TLC372-EP 增强型产品 Lincmos 双路差动比较器
This device is fabricated using LinCMOS™ technology and consists of two independent voltage comparators, each designed to operate from a single power supply. Operation from dual supplies is also possible if the difference between the two supplies is 4 V to 18 V. Each device features extremely high input impedance (typically greater than 1012), allowing direct interfacing with high-impedance sources. The outputs are n-channel open-drain configurations and can be connected to achieve positive-logic wired-AND relationships.
The TLC372 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 2000-V ESD rating using human-body-model (HBM) testing. However, care should be exercised in handling this device as exposure to ESD may result in a degradation of the device parametric performance.
The TLC372 is characterized for operation from -55°C to 125°C
| TLC372-EP | |
| Number of Channels | 2 |
| Iq per channel (Max) (mA) | 0.15 |
| Output Current (Min) (mA) | 6 |
| tRESP Low - to - High (us) | 0.2 |
| Output Type | Open Collector,Open Drain |
| VIO (25 deg C) (Max) (mV) | 5 |
| Pin/Package | 8SOIC |
| VICR (Min) (V) | 0 |
| VICR (Max) (V) | 14.5 |
| Vs (Min) (V) | 4 |
| Vs (Max) (V) | 16 |
| Operating Temperature Range (C) | -55 to 125 |
| Rating | HiRel Enhanced Produc |
TLC372-EP 特性
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of -55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product Change Notification
- Qualification Pedigree(1)
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 100 V Using Machine Model (C = 200 pF, R = 0)
- Single or Dual-Supply Operation
- Wide Range of Supply Voltages . . .4 V to 18 V
- Very Low Supply Current Drain . . .150 µA Typ at 5 V
- Fast Response Time . . . 200 ns Typ for TTL-Level Input Step
- Built-in ESD Protection
- High Input Impedance . . . 1012 Typ
- Extremely Low Input Bias Current. . .5 pA Typ
- Ultrastable Low Input Offset Voltage
- Input Offset Voltage Change at Worst-Case Input Conditions Typically 0.23 µV/Month, Including the First 30 Days
- Common-Mode Input Voltage Range Includes Ground
- Output Compatible With TTL, MOS, and CMOS
- Pin-Compatible With LM393
TLC372-EP 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| TLC372MDREP | ACTIVE | -55 to 125 | SOIC (D) | 8 | |||
| V62/06675-01XE | ACTIVE | -55 to 125 | SOIC (D) | 8 |
TLC372-EP 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| TLC372MDREP | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | TLC372MDREP | TLC372MDREP |
| V62/06675-01XE | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | V62/06675-01XE | V62/06675-01XE |
TLC372-EP 应用技术支持与电子电路设计开发资源下载
- TLC372-EP 数据资料 dataSheet 下载.PDF
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