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W7200 ARM 32bit Cortex M3 with hardwired TCP/IP, MAC & PHY

iMCU W7200 is the one-chip solution which integrates an Cortex-M3 core, 20KB SRAM and hardwired TCP/IP Core for high performance and easy development.
The TCP/IP core is a market-proven hardwired TCP/IP stack with an integrated Ethernet MAC & PHY. The Hardwired TCP/IP stack supports the TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE which has been used in various applications for years。

ARM 32-bit Cortex-M3  72MHz maximum frequency (1.25 DMIPS/MHz) 20KBytes Data Memory (RAM) 128KBytes Code Memory Low Power: Support Sleep, Stop and Standby modes 7 timers Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input 2 watchdog timers (Independent and Window) SysTick timer 24-bit down counter Full-duplex UART Programmable Watchdog Timer CRC calculation unit, 96-bit unique ID GPIO, SPI, USART and USB Interfaces 10BaseT/100BaseTX Ethernet PHY embedded

Hardwired TCP/IP Power down mode supported for saving power consumption Hardwired TCP/IP Protocols: TCP, UDP, ICMP, IPv4 ARP, IGMP, PPPoE, Ethernet Auto Negotiation (Full-duplex and half duplex), Auto MDI/MDIX ADSL connection with PPPoE Protocol with PAP/CHAP Authentication mode support 8 independent sockets which are running simultaneously 32Kbytes Data buffer for the Network Network status LED outputs (TX, RX, Full/Half duplex, Collision, Link, and Speed) Not supports IP fragmentation

功能框图

W7200 技术支持与电子电路设计开发资源下载

	LANGUAGE	Version 版本
W7200 数据手册Datasheet下载	English	1.0
W7200 开发板原理图与物料单	English	1.0
W7200 integrated driver	English	2012-02-02
W7200 Application Note Codes and Documents	English