Virtex-6 CXT FPGA 器件技术资料下载

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Virtex-6 Family Package/Device Pinout Files (ASCII) 。All package files are ASCII files in txt format.    
Virtex-6 FPGA User Guides
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Virtex-6 FPGA Packaging and Pinout Specifications

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

ver 2.4 15.84 MB
Virtex-6 FPGA SelectIO Resources User Guide

This guide describes the SelectIO™ resources available in all the Virtex®-6 devices.

ver 1.3 5.79 MB
ug362:Virtex-6 FPGA Clocking Resources User Guide

This guide describes the clocking resources available in all the Virtex®-6 devices, including the MMCM and Clock Buffers.

ver 2.1 2.0 MB
Virtex-6 FPGA Memory Resources User Guide

This guide describes the Virtex®-6 device block RAM and FIFO capabilities.

ver 1.6 2.35 MB
UG364:Virtex-6 FPGA Configurable Logic Block User Guide

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Virtex®-6 devices.

ver 1.2 1.81 MB
Virtex-6 FPGA GTX Transceivers User Guide

This guide describes the GTX transceivers available in all the Virtex®-6 FPGAs except the XC6VLX760.

ver 2.6 11.86 MB
Virtex-6 FPGA GTH Transceivers User Guide

This guide describes the GTH transceivers available in the Virtex®-6 HXT FPGAs.

5.4 MB ver 2.2
Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide

This guide describes the dedicated tri-mode Ethernet media access controller (TEMAC) available in all the Virtex®-6 FPGAs except the XC6VLX760.

ver 1.3 6.4 MB
UG517:Virtex-6 FPGA Integrated Block for PCI Express User Guide

This guide describes the function and operation of the Virtex®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This solution supports the legacy TRN interface for the customer user interface.

ver 5.1 12.33 MB
Virtex-6 FPGA DSP48E1 Slice User Guide

This guide describes the DSP48E1 slice in Virtex®-6 FPGAs and includes configuration examples.

ver 1.3 1.79 MB
Virtex-6 FPGA System Monitor User Guide

This guide describes the System Monitor functionality.

ver 1.1 2.83 MB
Virtex-6 FPGA GTX Transceiver Signal Integrity Simulation Kit (Synopsys HSPICE) User Guide

The Virtex®-6 FPGA GTX Transceiver Signal Integrity Simulation Kit for Synopsys HSPICE enables signal integrity simulations of a communication link between Virtex-6 FPGA GTX transceivers. This kit includes models of the line driver of the transmitter and the analog front end of the receiver of the GTX transceivers.

ver 1.1 2.22 MB
Virtex-6 FPGA GTX Transceiver Signal Integrity Simulation Kit User Guide For Mentor Graphics HyperLynx

This guide describes the Virtex®-6 FPGA GTX Transceiver Signal Integrity Simulation (SIS) Kit for Mentor Graphics HyperLynx.

ver 1.1.1 4.7 MB
Virtex-6 FPGA PCB Design Guide

This guide provides information on PCB design for Virtex®-6 devices, with a focus on strategies for making design decisions at the PCB and the interface level.

ver 1.2 10.2 MB
Virtex-6 FPGA Errata
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Virtex-6 FPGA LX760, LX550T, LX365T, LX240T, LX195T, LX130T, SX475T, and SX315T CES Errata

EN101: Errata for the Virtex®-6 FPGA LX760, LX550T, LX365T, LX240T, LX195T, LX130T, SX475T, and SX315T devices.

ver 1.9 243 KB
Virtex-6 FPGA LX, LXT, SXT, and HXT Production Errata

EN142: Errata for the Virtex®-6 FPGA LX, LXT, SXT, and HXT production devices.

ver 1.13 226 KB
Virtex-6 FPGA HX250T and HX380T CES Errata

EN145: Errata for the Virtex®-6 FPGA HX250T and HX380T CES devices.

ver 1.6 224 KB
Virtex-6 FPGA -1L Speed Grade LX75T, LX130T, LX195T, LX240T, LX365T, LX550T, LX760, SX315T, and SX475T Production Errata

EN154: Errata for the Virtex®-6 FPGA -1L speed grade LX75T, LX130T, LX195T, LX240T, LX365T, LX550T, LX760, SX315T, and SX475T devices.

ver 1.5 247 KB
Virtex-6 FPGA HX255T, HX380T, and HX565T CES Errata

EN157: Errata for the Virtex®-6 FPGA HX255T, HX380T, and HX565T CES devices.

ver 1.3 250 KB
Virtex-6 FPGA Customer Notices
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XCN09033 - Humidity Indicator Card (HIC) Change

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

ver 1.0 67 KB
XCN11015 - Virtex-6 FPGA: Built-In Synchronous FIFO Reset and Input Logic Reset

To inform Xilinx customers of corrections to the described behavior of specific function blocks within the Virtex®-6 FPGA. The affected function blocks include the built-in synchronous FIFO and the input logic registers.

ver 1.0 106 KB
XCN10032 - Virtex-6: GTX User Guide, Data Sheet (SYSMON DCLK) and JTAG ID Changes (PDF, , )

To inform Xilinx customers of changes to the Virtex®-6 FPGA user guide, data sheet and JTAG revision codes.

ver 1.0 135 KB
XCN11026 - Virtex-6 BRAM/FIFO Timing Issue (Quality Alert)(PDF, , )

The ISE® 11.x, 12.x and 13.1 TRCE/Timing Analyzer tools do not correctly analyze certain control signals and address lines of the Virtex®-6 36Kb BRAM (RAMB36E1), 18Kb BRAM (RAMB18E1), and 18Kb FIFO (FIFO18E1) when used in SDP, TDP, or ECC modes, potentially resulting in unreported setup and hold time violations. The unreported violations can result in read and write errors in silicon and are not reported in the unconstrained path report section of the timing report.

ver 1.0 29 KB
Virtex-6 FPGA Application Notes
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XAPP882 - SERDES Framer Interface Level 5 for Virtex-6 Devices

This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) in a Virtex®-6 XC6VLX240T FPGA.

设计文件:

ver 1.1 2.31 MB
XAPP887:PRC/EPRC: Data Integrity and Security Controller for Partial Reconfiguration

This application note describes a data integrity controller for partial reconfiguration (PRC) that can be included in any partially reconfigurable FPGA design to process partial bitstreams for data integrity

ver 1.0 688 KB
XAPP878 - MMCM Dynamic Reconfiguration

This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Virtex®-6 FPGA mixed-mode clock manager (MMCM) through its dynamic reconfiguration port.

设计文件:

ver 1.1 413 KB
XAPP1071 - Connecting Virtex-6 FPGAs to ADCs with Serial LVDS Interfaces and DACs with Parallel LVDS Interfaces

This application note describes how to utilize the dedicated deserializer(ISERDES) and serializer (OSERDES) functionalities in Virtex®-6 FPGAs to interface with analog-to-digital converters that have serial low-voltage differential signaling (LVDS) outputs and with digital-to-analog converters that have parallel LVDS inputs.

ver 1.0 1.46 MB

XAPP1073 - NSEU Mitigation in Avionics Applications

This application note provides background on NSEUs in SRAM-based FPGAs, mitigation techniques (with a focus on configuration memory) suggested by Xilinx, and an overview of calculating projected failures-in-time (FIT) rates at altitude.

ver 1.0 477 KB

XAPP880 - SFI-4.1 16-Channel SDR Interface with Bus Alignment Using Virtex-6 FPGAs

设计文件:

ver 1.0 1.85 MB
XAPP881 - Virtex-6 FPGA LVDS 4X Asynchronous Oversampling at 1.25 Gb/s

This application note uses Virtex®-6 FPGA SelectIO™ technology to perform 4X asynchronous oversampling at 1.25 Gb/s. The oversampling is accomplished using the ISERDESE1 primitive through the mixed-mode clock manager (MMCM) dedicated performance path.

设计文件:

ver 1.0.1 1.3 MB
XAPP886 - Interfacing QDR II SRAM Devices with Virtex-6 FPGAs

This application note presents a Verilog reference design that has been simulated, synthesized, and verified on hardware using Virtex®-6 FPGAs and QDR II SRAM two-word burst devices.

ver 1.0 311 KB
Virtex-6 FPGA Package Specifications
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FF1760 - Material Declaration Data Sheet (Standard Flip Chip BGA)

设计文件:

ver 1.1 68 KB
FFG1759 - Material Declaration Data Sheet

100% Material Declaration Data Sheet FFG1759 Package for Virtex®-6 FPGAs

设计文件:

ver 1.1 136 KB
FF1759 - Package Drawing (1759 Ball Flip-Chip BGA) ver 1.1 161 KB
FF484 - Material Declaration Data Shee。

100% Material Declaration Data Sheet

设计文件:

ver 1.1 84 KB
FF484 - Package Drawing (484 Ball Flip-Chip BGA) ver 1.1 201 KB
FF784 - Package Drawing (784 Ball Flip-Chip BGA) ver 1.1 222 KB
FFG1156 - Material Declaration Data Sheet (Pb-free Fine-Pitch BGA)

100% Material Declaration Data Sheet FFG1156

设计文件:

ver 1.1.1 169 KB
FF1156 - Material Declaration Data Sheet (Fine-Pitch BGA)

100% Material Declaration Data Sheet FF1156

设计文件:

ver 1.1.1 167 KB
FFG1760 - Material Declaration Data Sheet (Pb-free Flip-Chip BGA)

设计文件:

ver 1.1 68 KB
FF1154 - Package Drawing (1156 Ball Flip-Chip BGA) ver 1.0 139 KB
FF1155 - Package Drawing (1156 Ball Flip-Chip BGA) ver 1.0 150 KB
FF1156/FFG1156 - Package Drawing (Flip-Chip BGA) ver 1.0 150 KB
Virtex-6 FPGA Characterization Reports
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RPT135:Virtex-6 FPGA GTH Transceivers CEI-11G-SR, CEI-11G-MR (Low Swing) and CAUI Electrical Interface Characterization Report

This characterization report compares the electrical performance of the Virtex®-6 FPGA GTH transceivers against OIF-CEI-02.0, Common Electrical I/O (CEI)—Electrical and Jitter Interoperability agreements for 6 Gb/s and 11 Gb/s I/O and IEEE Std 802.3ba-2010 Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications.

ver 1.0 3.46 MB
RPT122:Virtex-6 FPGA GTX Transceiver CPRI Electrical Standard Characterization Summary Report

This protocol compatibility report compares the physical layer (PHY) electrical performance of the Virtex®-6 FPGA GTX transceiver against the Common Public Radio Interface (CPRI) specification, v4.1.

ver 1.0 2.6 MB
RPT121:Virtex-6 FPGA GTX Transceiver Characterization Report PCI Express 2.0 (2.5 and 5.0 Gb/s) Electrical Standard

This characterization report compares the electrical performance of the Virtex®-6 FPGA GTX transceiver against the PCI Express® Revision 2.0 specifications published in the PCI Express Base Specification, Revision 2.1 and the PCI Express Card Electromechanical Specification, Revision 2.0.

ver 1.0 3.25 MB
Virtex-6 FPGA GTX Transceiver XAUI Protocol Characterization Summary Report

This protocol characterization summary report compares the electrical performance of the Virtex®-6 FPGA GTX transceiver against the 10 Gb Attachment Unit Interface (XAUI) specifications.

ver 1.0 931 KB
Virtex-6 FPGA White Papers
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WP249 - SPI-4.2 Dynamic Phase Alignment

This document explains the operation of the SPI-4.2 Dynamic Phase Alignment (DPA) Sink Core for Virtex®-4, Virtex-5, Virtex-6, and 7 series FPGAs and provides the guidelines on how to use the SPI-4.2 DPA solution.

ver 1.3 605 KB
WP298 - Power Consumption at 40 and 45 nm

At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. Spartan®-6 and Virtex®-6 FPGAs offer lower power, simpler power systems and PCB complexity, better reliability, and lower system cost. This white paper details how Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex-6 (40 nm) FPGA families, achieving dramatic power reductions over previous generation devices.

ver 1.0 1.59 MB
WP359 - Accelerating System Designs Requiring High-Bandwidth Connectivity with Targeted Reference Designs

This white paper describes the Virtex®-6 FPGA Connectivity Kit (DK-V6-CONN-G) and the Spartan®-6 FPGA Connectivity Kit (DK-S6-CONN-G) that engineers can use to jump-start their connectivity-based designs.

ver 01 418 KB
WP360 - Xilinx FPGA Embedded Memory Advantages

The Virtex®-6 and Spartan®-6 architectures feature flexible internal memory resources that can be configured in a variety of different sizes. This white paper details the available features, illustrating the wide array of memory sizes available and shows the trade-off of using different resources to perform memory functions of different sizes.

ver 1.0 443 KB
WP368:Unlock New Levels of Productivity for Your Design Using ISE Design Suite 12

ISE® Design Suite v12 is the production-optimized tool suite for Virtex®-6 and Spartan®-6 FPGAs that delivers innovation in three critical areas of FPGA design: power reduction, productivity, and performance.

ver 1.0 509 KB
WP370:Reducing Switching Power with Intelligent Clock Gating

Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30% for Virtex®-6, Spartan®-6, Kintex™-7 and Virtex-7 FPGA designs.

ver 1.3 395 KB
WP375:High Performance Computing Using FPGAs

Advancements in silicon, software, and IP have proven Xilinx FPGAs to be the ideal solution for accelerating applications on high-performance embedded computers and servers. This white paper describes the various use models for applying FPGAs in High Performance Computing (HPC) systems.

ver 1.0 556 KB
WP379 - AXI4 Interconnect Paves the Way to Plug-and-Play IP

The AXI4 specification represents a major evolutionary step in interconnect technology for on-chip system design. The value of the AXI4 interconnect has many facets, beginning with an immediate gain in productivity derived from a unified IP interconnect standard that supplants legacy and custom interconnect architectures. The three interconnect protocols developed for the AXI4 standard (AXI4, AXI4-Lite, and AXI4-Stream interfaces) provide the flexibility to optimize an FPGA design for performance, throughput, latency, or area.

ver 1.0 376 KB
WP381 - Virtex-6 FPGA Routing Optimization Design Techniques

Xilinx continues to refine the place and route algorithms in each of the ISE® software releases and provides up-to-date information on additional design techniques to help customers optimize routing in their Virtex®-6 FPGA designs, making it easier to reach performance and power design goals and achieve next-generation bandwidth requirements.

ver 1.0 1.09 MB
WP382 - SerDes Channel Simulation in FPGAs Using IBIS-AMI

The IBIS Algorithmic Modeling Interface (IBIS-AMI) was developed to enable fast, accurate statistical and time-domain simulation of high-speed channels. It combines the ease of use and speed of standard IBIS signal integrity analysis with advanced communications analysis techniques.

ver 1.0 5.91 MB