AD9540 低抖动、基于DDS的时钟发生器和频率合成器

AD9540支持多种功能,包括信号合成和低抖动时钟发生,适合各种应用。该器件内置高性能PLL电路,包括灵活的200 MHz鉴频鉴相器和数字控制电荷泵电流。它还可以使低抖动、655 MHz CML模式(PECL兼容)输出驱动器具有可编程压摆率。器件支持最高2.7 GHz的外部VCO速率。片上400 MSPS DDS提供及精密的调谐分辨率和相位编程能力。信息通过一个串行I/O端口载入AD9540中,该端口的器件写入速度为25Mb/s。还可以对AD9540分频器模块进行编程,支持扩频时钟模式。

AD9540的额定工作温度范围为-40℃至+85℃扩展汽车应用温度范围。

应用
  • 为高性能数据转换器提供时钟
  • 基站时钟应用
  • 网络(SONET/SDH)时钟
  • 千兆以太网(GbE)时钟
  • 仪器仪表时钟电路
产品特点和性能优势
  • 内在抖动性能< 500 fs
  • 合成信号频率达2.7 GHz
  • 时钟信号发生频率达655 MHz
  • 25 Mb/s写入速度串行I/O控制
  • 200 MHz鉴频鉴相器输入
  • 400 MSPS DDS片上
    可编程边沿延迟,93 fs分辨率
    频率分辨率<2.33 µHz<2.33 µHz
  • 655 MHz可编程输入分频器用于鉴频鉴相器(÷M,N) {M,N =1..16}(可旁路)
  • 8个可编程内部时钟速率
  • 器件采用1.8 V电源供电
    I/O、CML驱动器和电荷泵输出采用3.3 V电源供电
  • 软件控制省电功能
  • 48引脚LFCSP封装
  • 可编程电荷泵电流(最高达4 mA)
时钟与定时
射频和微波
数据手册
文档备注
AD9540:  655 MHz Low Jitter Clock Generator Data Sheet (Rev. A)PDF 839 kB
应用笔记
文档备注
AN-1389: 引线框芯片级封装(LFCSP)的建议返修程序 (Rev. 0)PDF 652.16 K
AN-1389: Recommended Rework Procedure for the Lead Frame Chip Scale Package (LFCSP) (Rev. 0)PDF 133.7 K
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)PDF 227 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)PDF 291.7 K
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)PDF 0
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)PDF 221 kB
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)PDF 313 kB
AN-621: Programming the AD9832/AD9835PDF 202 kB
AN-557: An Experimenter's Project: (Rev. 0)PDF 368 kB
AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal Oscillator for the AD9850PDF 101 kB
AN-237: Choosing DACs for Direct Digital SynthesisPDF 1156 kB
AN-423: Amplitude Modulation of the AD9850 Direct Digital SynthesizerPDF 37 kB
AN-345: Grounding for Low-and-High-Frequency CircuitsPDF 455 kB
AN-342: Analog Signal-Handling for High Speed and AccuracyPDF 468 kB
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)PDF 115 kB
AN-280: Mixed Signal Circuit TechnologiesPDF 2101 kB
AN-605: Synchronizing Multiple AD9852 DDS-Based Synthesizers (Rev. 0)PDF 527 kB
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)PDF 170 kB
AN-587: Synchronizing Multiple AD9850/AD9851 DDS-Based Synthesizers (Rev. 0)PDF 116 kB
AN-772: 引脚架构芯片级封装(LFCSP)设计与制造指南 (Rev. 0)PDF 828 kB
AN-769: 基于AD9540产生多时钟输出 (Rev. 0)PDF 130 kB
AN-237: 放大器直接数字频率合成的DAC选型器应用漫谈 (Rev. 0)PDF 1156 kB
AN-953: 具可编程模数的直接数字频率合成器(DDS) (Rev. 0)PDF 99 kB
AN-873: ADF4xxx系列PLL频率合成器的锁定检测 (Rev. 0)PDF 0
AN-605: 同步多个基于DDS的频率合成器AD9852 (Rev. A)PDF 0
AN-953: Direct Digital Synthesis (DDS) with a Programmable Modulus (Rev. B)PDF 112 kB
AN-939: 利用AD9912的超奈奎斯特频率操作得到高RF输出信号 (Rev. 0)PDF 0
AN-927: 确定杂散来源是DDS/DAC还是其他器件(例如开关电源)[中文版] (Rev. 0)PDF 234 kB
AN-837: 基于DDS的时钟抖动性能与DAC重构滤波器性能的关系[中文版] (Rev. 0)PDF 416 kB
AN-772: A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP) (Rev. 0)PDF 439 kB
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)PDF 207 kB
AN-823: 时钟应用中的直接数字频率合成器[中文版] (Rev. 0)PDF 303 kB
AN-851: 一种WiMax双下变频IF采样接收机设计方案[中文版] (Rev. 0)PDF 421 kB
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev. 0)PDF 262 kB
AN-345: 低频和高频电路接地PDF 823 kB
AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版] (Rev. 0)PDF 808 kB
AN-501: 孔径不确定度与ADC系统性能[中文版] (Rev. A)PDF 227 kB
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)PDF 1679 kB
AN-741: 鲜为人知的相位噪声特性PDF 359 kB
AN-632: 利用AD9951 DDS作为ADN2812连续速率CDR的捷变参考时钟以提供数据速率 (Rev. 0)PDF 298 kB
AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous-Rate CDR (Rev. 0)PDF 138 kB
AN-621: AD9832/AD9835的编程 (Rev. 0)PDF 171 kB
AN-342: 高速、高精度处理模拟信号[中文版] (Rev. 0)PDF 466 kB
AN-557: 实验者项目: (Rev. 0)PDF 942 kB
AN-419: 用于完整的直接数字频率合成器AD9850的分立、低相位噪声、125MH晶振 (Rev. A)PDF 216 kB
AN-423: 直接数字频率合成器AD9850的幅度调制 (Rev. A)PDF 159 kB
AN-587: 同步多个基于DDS的频率合成器AD9850/AD9851 (Rev. 0)PDF 724 kB
AN-543: 利用ADSP-2181 DSP和AD9850直接数字频率合成器产生高质量、全数字RF频率调制 (Rev. A)
AN-543 - Monaural FM Transmitter AN-543 - Stereo FM Transmitter
PDF 335 kB
AN-543: High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 and the AD9850 DDS
AN-543 - Monaural FM Transmitter AN-543 - Stereo FM Transmitter
PDF 49.25 K
产品聚焦
文档备注
Introducing Digital Up/Down Converters: VersaCOMM™ Reconfigurable Digital ConvertersPDF 63 kB
订购信息
产品型号封装包装数量温度范围美金报价 100-499美金报价 1000+RoHS
AD9540BCPZ 量产48 ld LFCSP 7x7mm (5.1EP)OTH 260-40 至 85至15.3913.09Y
AD9540BCPZ-REEL7 量产48 ld LFCSP 7x7mm (5.1EP)REEL 750-40 至 85至15.3913.09Y
参考资料
AD9540:  655 MHz Low Jitter Clock Generator Data Sheet (Rev. A) ad9540
AN-1389: 引线框芯片级封装(LFCSP)的建议返修程序 (Rev. 0) ad9540
AN-1389: Recommended Rework Procedure for the Lead Frame Chip Scale Package (LFCSP) (Rev. 0) ad9856
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A) ad9220
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) ad9220
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0) ad9540
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0) ad9540
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0) ad9856
AN-621: Programming the AD9832/AD9835 ad9540
AN-557: An Experimenter's Project: (Rev. 0) ad9540
AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal Oscillator for the AD9850 ad9540
AN-237: Choosing DACs for Direct Digital Synthesis ad9856
AN-423: Amplitude Modulation of the AD9850 Direct Digital Synthesizer ad9540
AN-345: Grounding for Low-and-High-Frequency Circuits ad9220
AN-342: Analog Signal-Handling for High Speed and Accuracy ad1674
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0) ad9856
AN-280: Mixed Signal Circuit Technologies ad1674
AN-605: Synchronizing Multiple AD9852 DDS-Based Synthesizers (Rev. 0) ad9540
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0) ad9540
AN-587: Synchronizing Multiple AD9850/AD9851 DDS-Based Synthesizers (Rev. 0) ad9540
AN-772: 引脚架构芯片级封装(LFCSP)设计与制造指南 (Rev. 0) ad9540
AN-769: 基于AD9540产生多时钟输出 (Rev. 0) ad9540
AN-237: 放大器直接数字频率合成的DAC选型器应用漫谈 (Rev. 0) ad9540
AN-953: 具可编程模数的直接数字频率合成器(DDS) (Rev. 0) ad9540
AN-873: ADF4xxx系列PLL频率合成器的锁定检测 (Rev. 0) ad9540
AN-605: 同步多个基于DDS的频率合成器AD9852 (Rev. A) ad9540
AN-953: Direct Digital Synthesis (DDS) with a Programmable Modulus (Rev. B) ad9540
AN-939: 利用AD9912的超奈奎斯特频率操作得到高RF输出信号 (Rev. 0) ad9540
AN-927: 确定杂散来源是DDS/DAC还是其他器件(例如开关电源)[中文版] (Rev. 0) ad9540
AN-837: 基于DDS的时钟抖动性能与DAC重构滤波器性能的关系[中文版] (Rev. 0) ad9540
AN-772: A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP) (Rev. 0) ad9856
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0) ad9540
AN-823: 时钟应用中的直接数字频率合成器[中文版] (Rev. 0) ad9540
AN-851: 一种WiMax双下变频IF采样接收机设计方案[中文版] (Rev. 0) ad9540
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev. 0) ad9856
AN-345: 低频和高频电路接地 ad9540
AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版] (Rev. 0) ad9540
AN-501: 孔径不确定度与ADC系统性能[中文版] (Rev. A) ad9540
AN-741: Little Known Characteristics of Phase Noise (Rev. 0) ad9221
AN-741: 鲜为人知的相位噪声特性 ad9540
AN-632: 利用AD9951 DDS作为ADN2812连续速率CDR的捷变参考时钟以提供数据速率 (Rev. 0) ad9540
AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous-Rate CDR (Rev. 0) ad9540
AN-621: AD9832/AD9835的编程 (Rev. 0) ad9540
AN-342: 高速、高精度处理模拟信号[中文版] (Rev. 0) ad9540
AN-557: 实验者项目: (Rev. 0) ad9540
AN-419: 用于完整的直接数字频率合成器AD9850的分立、低相位噪声、125MH晶振 (Rev. A) ad9540
AN-423: 直接数字频率合成器AD9850的幅度调制 (Rev. A) ad9540
AN-587: 同步多个基于DDS的频率合成器AD9850/AD9851 (Rev. 0) ad9540
AN-543: 利用ADSP-2181 DSP和AD9850直接数字频率合成器产生高质量、全数字RF频率调制 (Rev. A) ad9540
AN-543 - Monaural FM Transmitter ad9540
AN-543: High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 and the AD9850 DDS ad9540
AN-543 - Monaural FM Transmitter ad9540
Introducing Digital Up/Down Converters: VersaCOMM™ Reconfigurable Digital Converters ad9856
Basics of Designing a Digital Radio Receiver (Radio 101) ad9856
Digital Up/Down Converters: VersaCOMM™ White Paper ad9856