AD9640 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter

The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-to-digital converter (ADC). The AD9640 is designed to support communications applications where low cost, small size, and versatility are desired. Integrated dual 14-bit, 80/105/125/150 MSPS ADC. Fast overrange detect and signal monitor with serial output. Signal monitor block with dedicated serial output mode. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 450 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. A standard serial port interface that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode. Pin compatibility with the AD9627, AD9627-11, and the AD9600 for a simple migration from 14 bits to 12 bits, 11 bits, or 10 bits.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compen-sate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The AD9640 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.

In addition, the programmable threshold detector allows moni-toring of the incoming signal power using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly turn down the system gain to avoid an overrange condition.

The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.

The ADC output data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.

The AD9640 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

Product Highlights

Integrated dual 14-bit, 80/105/125/150 MSPS ADC.
Fast overrange detect and signal monitor with serial output.
Signal monitor block with dedicated serial output mode.
Proprietary differential input that maintains excellent SNR performance for input frequencies up to 450 MHz.
Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
A standard serial port interface that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode.
Pin compatibility with the AD9627, AD9627-11, and the AD9600 for a simple migration from 14 bits to 12 bits, 11 bits, or 10 bits.

Applications

Communications
Diversity radio systems
Multimode digital receivers GSM, EDGE, WCDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications

产品特点和性能优势

信噪比(SNR)：71.8 dBc（72.8 dBFS，至70 MHz、125 MSPS）
无杂散动态范围(SFDR)：85 dBc (至70 MHz、125 MSPS)
低功耗：750 mW (125 MSPS)
信噪比(SNR)：71.6 dBc（72.6 dBFS，至70 MHz、150 MSPS）
无杂散动态范围(SFDR)：84 dBc (至70 MHz、150 MSPS)
低功耗：820 mW (150 MSPS)
1.8 V模拟电源供电

1.8 V至3.3V CMOS输出电源或1.8 V LVDS输出电源
1至8整数输入时钟除法器
中频采样频率达450 MHz
ADC内部基准电压源
集成ADC采样保持输入
灵活的模拟输入范围：1 V p-p至2 V p-p
欲了解更多特性，请参考数据手册

模数转换器 (ADC)

高速信号处理

宽带RF 信号处理解决方案

AD9640 IBIS Models

数据手册

文档	备注
AD9640: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet (Rev. B)	PDF 1448 kB

应用笔记

文档	备注
AN-878: High Speed ADC SPI Control Software (Rev. A)	PDF 585 kB
AN-808: CDMA2000多载波系统可行性研究 (Rev. 0)	PDF 0
AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual (Rev. 0)	PDF 2124 kB
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)	PDF 985 kB
AN-282: Fundamentals of Sampled Data Systems	PDF 2131 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)	PDF 291.7 K
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0)	PDF 203 kB
AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)	PDF 363 kB
AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. B)	PDF 401 kB
AN-345: Grounding for Low-and-High-Frequency Circuits	PDF 455 kB
AN-835: 高速ADC测试和评估 (Rev. 0)	PDF 1916 kB
AN-1234: 双中频增益模块ADL5534与高速ADC AD9640的接口 (Rev. B)	PDF 208 kB
AN-1234: Interfacing the ADL5534 Dual IF Gain Block to the AD9640 High Speed ADC (Rev. B)	PDF 208 kB
AN-1142: 高速ADC PCB布局布线技巧 (Rev. 0)	PDF 392 kB
AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)	PDF 392 kB
AN-878: 高速ADC SPI控制软件[中文版] (Rev. A)	PDF 630 kB
AN-282: 采样数据系统基本原理[中文版] (Rev. A)	PDF 1559 kB
AN-737: 如何用ADIsimADC完成ADC建模 (Rev. B)	PDF 373 kB
AN-737: How ADIsimADC Models an ADC (Rev. B)	PDF 373 kB
AN-807: 多载波WCDMA的可行性 (Rev. 0)	PDF 969 kB
AN-807: Multicarrier WCDMA Feasibility (Rev. 0)	PDF 969 kB
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)	PDF 1535 kB
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)	PDF 1535 kB
AN-827: 放大器与开关电容ADC接口的匹配方法[中文版] (Rev. 0)	PDF 783 kB
AN-905: VisualAnalog™转换器评估工具1.0版用户手册 (Rev. 0)	PDF 2124 kB
AN-935: ADC变压器耦合前端设计[中文版] (Rev. 0)	PDF 448 kB
AN-812: 基于微控制器的串行端口接口(SPI®)启动电路 (Rev. 0) Software Download (zip, 21,702,560 bytes)	PDF 309 kB
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (Rev. 0) Software Download (zip, 21,702,560 bytes)	PDF 441 kB
AN-851: 一种WiMax双下变频IF采样接收机设计方案[中文版] (Rev. 0)	PDF 421 kB
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev. 0)	PDF 262 kB
AN-715: 走近IBIS模型：什么是IBIS模型？它们是如何生成的？ (Rev. 0)	PDF 370 kB
AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (Rev. 0)	PDF 370.2 K
AN-345: 低频和高频电路接地	PDF 823 kB
AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版] (Rev. 0)	PDF 808 kB
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)	PDF 1679 kB
AN-741: 鲜为人知的相位噪声特性	PDF 359 kB

产品聚焦

文档	备注
Leading Inside Advertorials: Data Converter Function Can Help Solve Cost and Size Design Challenges in 3G and 4G Wireless Infrastructure	PDF 94 kB

订购信息

产品型号	封装	包装数量	温度范围	美金报价 100-499	美金报价 1000+	RoHS
AD80192ABCPZ-155 量产	64 ld LFCSP (9x9mm, 7.10 exposed pad)	OTH 260	-40 至 85至	0	0	Y
AD9640ABCPZ-105 量产	64 ld LFCSP (9x9mm, 7.5mm exposed pad)	OTH 260	-40 至 85至	73.22	62.24	Y
AD9640ABCPZ-125 量产	64 ld LFCSP (9x9mm, 7.5mm exposed pad)	OTH 260	-40 至 85至	87.51	74.38	Y
AD9640ABCPZ-150 量产	64 ld LFCSP (9x9mm, 7.5mm exposed pad)	OTH 260	-40 至 85至	116.08	98.67	Y
AD9640ABCPZ-80 量产	64 ld LFCSP (9x9mm, 7.5mm exposed pad)	OTH 260	-40 至 85至	44.65	37.95	Y
AD9640ABCPZRL7-105 停产	64 ld LFCSP (9x9mm, 7.5mm exposed pad)	REEL 750		0	0	Y
AD9640ABCPZRL7-125 量产	64 ld LFCSP (9x9mm, 7.5mm exposed pad)	REEL 750	-40 至 85至	87.51	74.38	Y
AD9640ABCPZRL7-80 量产	64 ld LFCSP (9x9mm, 7.5mm exposed pad)	REEL 750	-40 至 85至	44.65	37.95	Y