时钟分配

型号Number of OutputsMax FrequencyInput SpanNoise FloorJitterOutputCommentsPackages
LTC6950514000.8 to 1.5Vpp-1550.0184x LVPECL, 1x LVDS/CMOS1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution5x9 QFN-48
LTC6951525000.8 to 1.5Vpp-1650.1154x CML, 1x LVDSUltralow Jitter Multi-Output Clock Synthesizer with Integrated VCO5x7 QFN-40
LTC6951-1527000.8 to 1.5Vpp-1650.1154x CML, 1x LVDSUltralow Jitter Multi-Output Clock Synthesizer with Integrated VCO5x7 QFN-40
LTC6954-1318000.2Vpp to 1.5Vpp-1680.023X LVPECLLow Phase Noise, Triple Output Clock Distribution Divider/Driver, Three LVPECL outputs4x7 QFN-36
LTC6954-2314000.2Vpp to 1.5Vpp-1680.022X LVPECL, 1X LVDS/CMOSLow Phase Noise, Triple Output Clock Distribution Divider/Driver, Two LVPECL and one LVDS/CMOS4x7 QFN-36
LTC6954-3314000.2Vpp to 1.5Vpp-1680.021X LVPECL, 2XLVDS/CMOS outputsLow Phase Noise, Triple Output Clock Distribution Divider/Driver, One LVPECL and two LVDS/CMOS outputs4x7 QFN-36
LTC6954-4314000.2Vpp to 1.5Vpp-1680.023X LVDS/CMOSLow Phase Noise, Triple Output Clock Distribution Divider/Driver, Three LVDS/CMOS outputs4x7 QFN-36
LTC6957-123000.2 to 2.0Vpp-1610.045LVPECLLow Phase Noise, Dual Output Buffer/Driver/Logic Converter, LVPECL Logic Outputs3x3 DFN-12,MS-12
LTC6957-223000.2 to 2.0Vpp-159.50.067LVDSLow Phase Noise, Dual Output Buffer/Driver/Logic Converter, LVDS Logic Outputs3x3 DFN-12,MS-12
LTC6957-323000.2 to 2.0Vpp-1610.053In Phase CMOSLow Phase Noise, Dual Output Buffer/Driver/Logic Converter, CMOS Logic, In-Phase Outputs3x3 DFN-12,MS-12
LTC6957-423000.2 to 2.0Vpp-1610.053Complementary CMOSLow Phase Noise, Dual Output Buffer/Driver/Logic Converter, CMOS Logic, Complementary Outputs3x3 DFN-12,MS-12