74ALVC16835ADGG: 18位寄存驱动器(3态)

74ALVC16835A是18位寄存驱动器。数据流由低电平有效输出使能(OE)、低电平有效锁存使能(LE)和时钟输入(CP)进行控制。

LE为低电平时,A到Y的数据流是透明的。LE为高电平且CP保持在低电平或高电平时,数据会被锁存;只要CP从低电平瞬变至高电平,A数据就会被存储在锁存器/触发器中。

OE为低电平时,输出处于激活状态。OE为高电平时,输出转为高阻抗关断状态。OE输入的操作不会影响锁存器/触发器的状态。

为确保上电或掉电期间的高阻抗状态,OE应当通过上拉电阻连接到VCC;最低电阻值由驱动器灌入电流的能力确定。

74ALVC16835ADGG: 产品结构框图
Outline 3d SOT364-1
数据手册 (1)
名称/描述Modified Date
18-bit registered driver (3-state) (REV 6.0) PDF (119.0 kB) 74ALVC16835A [English]14 Mar 2014
应用说明 (6)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]15 Sep 1995
手册 (3)
名称/描述Modified Date
Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English]10 Jul 2015
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic thin shrink small outline package; 56 leads; body width 6.1 mm (REV 1.0) PDF (506.0 kB) SOT364-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 4.0) PDF (248.0 kB) SOT364-1_118 [English]15 Apr 2013
支持信息 (1)
名称/描述Modified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS
订购信息
型号状态Family功能VCC (V)说明Logic switching levelsPackage versionOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74ALVC16835ADGGActiveALVCLatches/registered drivers1.65 - 3.618-bit registered driver (3-State)LVTTLSOT364-1+/- 24418low-40~859321.0TSSOP5656
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74ALVC16835ADGGSOT364-1SSOP-TSSOP-VSO-WAVEReel 13" Q1/T1Active74ALVC16835ADGG:11 (9352 673 33118)74ALVC16835A74ALVC16835ADGGweek 40, 2005123.83.872.58E811
Bulk PackActive74ALVC16835ADGG,11 (9352 673 33112)74ALVC16835A74ALVC16835ADGGweek 40, 2005123.83.872.58E811
18-bit registered driver (3-state) 74ALVC16835ADGG
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
A metastability primer 74AHC573PW
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
Low voltage CMOS family - LVC 74LVC_H_245A_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
alv835a IBIS model 74ALVC16835ADGG
plastic thin shrink small outline package; 56 leads; body width 6.1 mm pcf8576d_automotive
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... pcf8576d_automotive
74AVCM162836DGG
74LVT16652A