74ALVCH16245DL: 16位收发器,具有方向针脚;3态

74ALVC16245;74ALVCH16245是16位收发器,在发送和接收方向上都具有非反相3态总线兼容输出。

74ALVC16245;74ALVCH16245具有两个可实现轻松级联的输出使能输入(针脚nOE)和两个可实现方向控制的发送输入或接收输入(针脚nDIR)。针脚nOE控制输出,因此总线可以得到有效隔离。该器件可用作两个8位收发器或一个16位收发器。

74ALVCH16245具有有源总线保持电路,提供该电路是为了使闲置或浮动数据输入保持在有效逻辑电平。该器件因此特性而无需外部上拉或下拉电阻。

74ALVCH16245DL: 产品结构框图
Outline 3d SOT370-1
数据手册 (1)
名称/描述Modified Date
16-bit transceiver with direction pin; 3-state (REV 3.0) PDF (97.0 kB) 74ALVC_ALVCH16245 [English]12 May 2004
应用说明 (5)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]15 Sep 1995
手册 (2)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic shrink small outline package; 48 leads; body width 7.5 mm (REV 1.0) PDF (482.0 kB) SOT370-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
Standard product orientation 12NC ending 118 (REV 2.0) PDF (87.0 kB) SOT370-1_118 [English]19 Apr 2013
支持信息 (2)
名称/描述Modified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS
订购信息
型号状态Family功能VCC (V)说明Logic switching levelsOutput drive capabilityPackage versiontpd (ns)No of bitsfmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74ALVCH16245DLActiveALVCTransceivers1.65 - 3.616-bit transceiver with bus hold (3-state)TTL+/- 24SOT370-11.916150low8825.0SSOP4848
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74ALVCH16245DLSOT370-1SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1Active74ALVCH16245DL,118 (9352 604 42118)ALVCH1624574ALVCH16245DLweek 13, 2005123.83.872.58E811
Bulk PackActive74ALVCH16245DL,112 (9352 604 42112)ALVCH1624574ALVCH16245DLweek 13, 2005123.83.872.58E811
16-bit transceiver with direction pin; 3-state 74ALVCH16245DL
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
alvch16245 IBIS model 74ALVCH16245DL
plastic shrink small outline package; 48 leads; body width 7.5 mm gtl2000dl
Footprint for reflow soldering 74HC_T_595_Q100
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
Standard product orientation 12NC ending 118 gtl2000dl
74LVTN16245B
74LVT162245B