74AUP1G02GW: 低功耗2输入或非门

74AUP1G02提供单路2输入或非功能。

所有输入处的施密特触发器动作使电路容许整个0.8 V至3.6 V VCC范围内较慢的输入上升和下降时间。

该器件可确保整个0.8 V至3.6 V VCC范围内的极低静态和动态功耗。

该器件完全针对使用IOFF的局部掉电应用设计。IOFF电路可禁用输出,防止掉电时破坏性回流电流通过该器件。

74AUP1G02GW: 产品结构框图
Outline 3d SOT353-1
数据手册 (1)
名称/描述Modified Date
Low-power 2-input NOR-gate (REV 7.0) PDF (206.0 kB) 74AUP1G02 [English]21 Jan 2015
应用说明 (3)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
手册 (3)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic thin shrink small outline package; 5 leads; body width 1.25 mm (REV 1.0) PDF (223.0 kB) SOT353-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
TSSOP5; Reel pack; SMD, 7"; Q3 Reversed product orientation; Orderable part number ending, 125 or H; Ordering code... (REV 1.0) PDF (257.0 kB) SOT353-1_125 [English]15 May 2013
支持信息 (1)
名称/描述Modified Date
MAR_SOT353 Topmark (REV 1.0) PDF (103.0 kB) MAR_SOT353 [English]03 Jun 2013
IBIS
订购信息
型号状态Family功能VCC (V)Logic switching levels说明类型Package versionOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP1G02GWActiveAUPNOR gates1.1 - 3.6CMOSsingle 2-input NOR gateNOR gatesSOT353-1+/- 1.98.3701ultra low-40~12530979.2179TSSOP55
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74AUP1G02GWSOT353-1Reel 7" Q3/T4, ReverseActive74AUP1G02GW,125 (9352 789 99125)pB74AUP1G02GWAlways Pb-free0.03.293.04E811
Low-power 2-input NOR-gate 74AUP1G02GW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT353 Topmark 74LVC1G17_Q100
74AUP1G02 IBIS model 74AUP1G02GW
plastic thin shrink small outline package; 5 leads; body width 1.25 mm 74LVC1G17_Q100
TSSOP5; Reel pack; SMD, 7"; Q3 Reversed product orientation; Orderable part number ending, 125 or H; Ordering code... 74LVC1G17_Q100
74HC_T_2G32
XC7SH14