74AUP1G18GM: 低功耗2选1解复用器,具有3态取消选定输出

74AUP1G18提供带3态输出的2选1非反相解复用器。74AUP1G18缓冲输入针脚(A)上的数据并将其传输到输出1Y或2Y,具体取决于选择输入针脚(S)的状态是低电平还是高电平。

所有输入处的施密特触发器动作使电路能容许整个0.8 V至3.6 V的VCC范围内较慢的输入上升和下降时间。该器件可确保整个0.8 V至3.6 V的CC范围内极低的静态和动态功耗。

该器件完全针对使用IOFF的局部掉电应用设计。IOFF电路可禁用输出,防止断电时破坏性回流电流通过该器件。

74AUP1G18GM: 产品结构框图
Outline 3d SOT886
数据手册 (1)
名称/描述Modified Date
Low-power 1-of-2 demultiplexer with 3-state deselected output (REV 5.0) PDF (209.0 kB) 74AUP1G18 [English]03 Jul 2012
应用说明 (4)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English]30 Dec 2010
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
手册 (3)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm (REV 1.0) PDF (189.0 kB) SOT886 [English]08 Feb 2016
包装 (2)
名称/描述Modified Date
XSON6; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering... (REV 2.0) PDF (205.0 kB) SOT886_115 [English]23 Apr 2013
XSON6; reel pack; standard product orientation; 12NC ending 132 (REV 1.0) PDF (180.0 kB) SOT886_132 [English]28 Nov 2012
支持信息 (2)
名称/描述Modified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]30 Sep 2013
MAR_SOT886 Topmark (REV 1.0) PDF (73.0 kB) MAR_SOT886 [English]03 Jun 2013
IBIS
订购信息
型号状态FamilyVCC (V)功能Logic switching levels说明Output drive capability (mA)Package versiontpd (ns)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP1G18GMActiveAUP1.1 - 3.6Decoders/demultiplexersCMOS1-to-2 demultiplexer (3-state)1.9/-1.9SOT8863.2ultra low-40~1252906.5145XSON66
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74AUP1G18GMSOT886Reflow_Soldering_ProfileReel 7" Q1/T1, Q3/T4Active74AUP1G18GM,132 (9352 799 53132)pW74AUP1G18GMAlways Pb-free0.03.293.04E811
Reel 7" Q1/T1Active74AUP1G18GM,115 (9352 799 53115)pW74AUP1G18GMAlways Pb-free0.03.293.04E811
Low-power 1-of-2 demultiplexer with 3-state deselected output 74AUP1G18GW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
MicroPak soldering information NTS0102_Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT886 Topmark prtr5v0u2f
aup1g18 IBIS model 74AUP1G18GW
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm prtr5v0u2f
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
XSON6; reel pack; standard product orientation; 12NC ending 132 NCX2200GM
XSON6; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering... prtr5v0u2f
74LVC1G18
BGU8007