74AUP2G17GW: 低功耗双路施密特触发器

74AUP2G17提供两个施密特触发缓冲器。该器件能够将缓慢变化的输入信号转换成清晰无抖动的输出信号。

该器件可确保整个0.8 V至3.6 V VCC范围内的极低静态和动态功耗。

该器件完全适合使用IOFF的局部掉电应用。IOFF电路可禁用输出,防止掉电时破坏性回流电流通过该器件。

输入针对正和负向信号在不同点进行切换。正电压VT+和负电压VT-之差定义为输入迟滞电压VH.

74AUP2G17GW: 产品结构框图
SOT363
数据手册 (1)
名称/描述Modified Date
Low-power dual Schmitt trigger (REV 6.0) PDF (208.0 kB) 74AUP2G17 [English]04 Dec 2012
应用说明 (3)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
手册 (3)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic surface-mounted package; 6 leads (REV 1.0) PDF (246.0 kB) SOT363_1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (188.0 kB) SOT363_125 [English]20 Nov 2012
支持信息 (3)
名称/描述Modified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]30 Sep 2013
Wave Soldering Profile (REV 1.0) PDF (20.0 kB) WAVE_SOLDERING_PROFILE [English]30 Sep 2013
MAR_SOT363 Topmark (REV 1.0) PDF (104.0 kB) MAR_SOT363 [English]03 Jun 2013
IBIS
订购信息
型号状态Family功能VCC (V)Logic switching levels说明Output drive capability (mA)Package versiontpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP2G17GWActiveAUPSchmitt-triggers1.1 - 3.6CMOSdual buffer Schmitt-trigger+/- 1.9SOT3637.8702ultra Low-40~12526438.6153TSSOP66
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74AUP2G17GWSOT363Reflow_Soldering_Profile Wave_Soldering_Profile
Reflow_Soldering_Profile Wave_Soldering_Profile
Reel 7" Q3/T4, ReverseActive74AUP2G17GW,125 (9352 799 91125)pV74AUP2G17GWAlways Pb-free0.03.293.04E811
Low-power dual Schmitt trigger 74AUP2G17GW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT363 Topmark BSS84AKS
aup2g17 IBIS model 74AUP2G17GW
plastic surface-mounted package; 6 leads BSS84AKS
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
Tape reel SMD; reversed product orientation 12NC ending 125 74LVC2G17_Q100
74LVC2G17
BFU520Y