74AUP2G241DC: 低功耗双路缓冲器/线路驱动器;3态

74AUP2G241提供带3态输出的双路非反相缓冲器/线路驱动器。3态输出通过输出使能输入1OE和2OE控制。针脚1OE处的高电平使输出1Y呈高阻抗关断状态。针脚2OE处的低电平使输出2Y呈高阻抗关断状态。

所有输入处的施密特触发器动作使电路容许整个0.8 V至3.6 V VCC范围内较慢的输入上升和下降时间。

该器件可确保整个0.8 V至3.6 V VCC范围内的极低静态和动态功耗。

该器件完全适合使用IOFF的局部掉电应用。IOFF电路可禁用输出,防止掉电时破坏性回流电流通过该器件。

该器件具有输入禁用功能,它允许浮动输入信号。输出使能输入OE为高电平时,输入1A处于禁用状态。输出使能输入2OE为高电平时,输入2A处于禁用状态。

74AUP2G241DC: 产品结构框图
Outline 3d SOT765-1
数据手册 (1)
名称/描述Modified Date
Low-power dual buffer/line driver; 3-state (REV 7.0) PDF (302.0 kB) 74AUP2G241 [English]11 Feb 2013
应用说明 (3)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
手册 (3)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic very thin shrink small outline package; 8 leads; body width 2.3 mm (REV 1.1) PDF (245.0 kB) SOT765-1 [English]05 Jul 2016
包装 (1)
名称/描述Modified Date
VSSOP8; Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... (REV 5.0) PDF (210.0 kB) SOT765-1_125 [English]03 May 2013
IBIS
订购信息
型号状态Family功能VCC (V)Logic switching levels说明Output drive capability (mA)Package versionfmax (MHz)No of bitstpd (ns)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP2G241DCActiveAUPBuffers/inverters/drivers1.1 - 3.6CMOSdual buffer/line driver (3-state)+/- 1.9SOT765-17024.3ultra low-40~12520334.1113VSSOP88
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74AUP2G241DCSOT765-1Reel 7" Q3/T4, ReverseActive74AUP2G241DC,125 (9352 807 38125)p4174AUP2G241DCAlways Pb-free0.03.293.04E811
Low-power dual buffer/line driver; 3-state 74AUP2G241GT
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
aup2g241 IBIS model 74AUP2G241GT
plastic very thin shrink small outline package; 8 leads; body width 2.3 mm 74LVC3G17_Q100
VSSOP8; Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... 74LVC3G17_Q100
74AUP2G241
XC7WT14