74AUP2G57DP: Low-power dual PCB configurable multiple function gate

The 74AUP2G57 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

74AUP2G57DP: 产品结构框图
sot552-1_3d
数据手册 (1)
名称/描述Modified Date
Low-power dual PCB configurable multiple function gate (REV 2.0) PDF (221.0 kB) 74AUP2G57 [English]02 Dec 2015
手册 (5)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Dual PCB configurable logic for more ways to save space and lower cost (REV 1.0) PDF (3.7 MB) 75017617_1 [English]10 Nov 2014
NXP® Dual PCB Configurable Logic (REV 1.0) PDF (3.0 MB) 75017615 [English]07 Nov 2014
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic thin shri small outline package; 10 leads; body width 3 mm (REV 1.1) PDF (256.0 kB) SOT552-1 [English]07 Jun 2016
包装 (1)
名称/描述Modified Date
TSSOP10; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (269.0 kB) SOT552-1_118 [English]16 Apr 2013
支持信息 (3)
名称/描述Modified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]30 Sep 2013
Wave Soldering Profile (REV 1.0) PDF (20.0 kB) WAVE_SOLDERING_PROFILE [English]30 Sep 2013
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS
订购信息
型号状态Family功能VCC (V)类型Logic switching levels说明Output drive capability (mA)Package versiontpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP2G57DPActiveAUPdual configurable gate; Schmitt trigger1.1 - 3.6Configurable gatesCMOSConfigurable+/- 1.9SOT552-18.7702ultra low-40~12512030.0TSSOP1010
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期MSLMSL LF
74AUP2G57DPSOT552-1Reflow_Soldering_Profile SSOP-TSSOP-VSO-WAVE
Reflow_Soldering_Profile SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1Active74AUP2G57DPJ (9353 044 71118)aC74AUP2G57DPAlways Pb-free11
Reel 7" Q3/T4, ReverseWithdrawn74AUP2G57DPH (9353 044 71125)aC74AUP2G57DPAlways Pb-free11
Low-power dual PCB configurable multiple function gate 74AUP2G57GU
電圧レベルシフタ 74AVC16245DGG-Q100
Dual PCB configurable logic for more ways to save space and lower cost 74AUP2G57GF
NXP® Dual PCB Configurable Logic 74AUP2G98GU
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
74AUP2G57 IBIS model 74AUP2G57GU
plastic thin shri small outline package; 10 leads; body width 3 mm 74AXP2T08DP-Q100
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
TSSOP10; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... 74AXP2T08DP-Q100
74AVCM162836DGG
PCA9633