74AUP3G17GM: Low-power triple Schmitt trigger
The 74AUP3G17 provides three Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.
74AUP3G17GM: 产品结构框图
Outline 3d SOT902-2
数据手册 (1)
| 名称/描述 | Modified Date |
|---|---|
| Low-power triple Schmitt trigger (REV 2.0) PDF (220.0 kB) 74AUP3G17 [English] | 12 Oct 2016 |
应用说明 (2)
| 名称/描述 | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
手册 (3)
| 名称/描述 | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
选型工具指南 (2)
| 名称/描述 | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
封装信息 (1)
| 名称/描述 | Modified Date |
|---|---|
| Plastic extremely thin quad flat package; no leads; 8 terminals (REV 1.3) PDF (206.0 kB) SOT902-2 [English] | 14 Jul 2016 |
包装 (1)
| 名称/描述 | Modified Date |
|---|---|
| XQFN8(U); Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... (REV 1.0) PDF (201.0 kB) SOT902-2_125 [English] | 02 May 2013 |
IBIS
- 74AUP3G17 IBIS model (REV 1.0) ibs AUP3G17 12/14/2015
订购信息
| 型号 | 状态 | VCC (V) | Family | Logic switching levels | 说明 | Output drive capability (mA) | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP3G17GM | Active | 1.1 - 3.6 | AUP | CMOS | triple buffer Schmitt-trigger | +/- 1.9 | 4.7 | 70 | 3 | ultra low | -40~125 | 251 | 128.0 | XQFN8 | 8 | SOT902-2 |
封装环保信息
| 产品编号 | 封装说明 | Outline Version | 回流/波峰焊接 | 包装 | 产品状态 | 部件编号订购码 (12NC) | Marking | 化学成分 | RoHS / 无铅 / RHF | 无铅转换日期 | EFR | IFR(FIT) | MTBF（小时） | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP3G17GM | | SOT902-2 | Reel 7" Q3/T4, Reverse | Active | 74AUP3G17GM,125 (9352 814 44125) | Standard Marking | 74AUP3G17GM |    | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 |
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- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
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- 電圧レベルシフタ 74AVC16245DGG-Q100
- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- 74AUP3G17 IBIS model 74AUP3G17GT
- Plastic extremely thin quad flat package; no leads; 8 terminals pca9509agm
- XQFN8(U); Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... pca9509agm
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