74LV00DB: 四路2输入与非门

74LV00是低压硅栅CMOS器件,与74HC00和74HCT00针脚和功能兼容。

74LV00提供四路2输入与非功能。

74LV00DB: 产品结构框图
Outline 3d SOT337-1
数据手册 (1)
名称/描述Modified Date
Quad 2-input NAND gate (REV 4.0) PDF (172.0 kB) 74LV00 [English]09 Dec 2015
应用说明 (1)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
手册 (2)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic shrink small outline package; 14 leads; body width 5.3 mm (REV 1.0) PDF (295.0 kB) SOT337-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
Standard product orientation 12NC ending 118 (REV 1.0) PDF (86.0 kB) SOT337-1_118 [English]04 Apr 2013
支持信息 (2)
名称/描述Modified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
SPICE
订购信息
型号状态Family功能VCC (V)类型Logic switching levels说明Package versionOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LV00DBActiveLVNAND gates1.0 - 5.5NAND gatesTTLquad 2-input NAND gateSOT337-1+/- 127304low-40~12515640.0SSOP1414
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74LV00DBSOT337-1SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1Active74LV00DB,118 (9351 701 30118)LV0074LV00DBweek 12, 2005144.910.239.78E711
Bulk PackActive74LV00DB,112 (9351 701 30112)LV0074LV00DBweek 12, 2005144.910.239.78E711
Quad 2-input NAND gate 74LV00PW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
lv Spice model 74LV74PW
plastic shrink small outline package; 14 leads; body width 5.3 mm 74LVC32A_Q100
Footprint for reflow soldering 74HC_T_595_Q100
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
Standard product orientation 12NC ending 118 74LVC32A_Q100
74LVC132A
74LV164