74LVT02D: 3.3 V Quad 2-input NOR gate

The 74LVT02 is a quad 2-input NOR gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

74LVT02D: 产品结构框图
sot108-1_3d
数据手册 (1)
名称/描述Modified Date
3.3 V Quad 2-input NOR gate (REV 2.0) PDF (91.0 kB) 74LVT02 [English]15 Aug 1996
应用说明 (7)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English]02 Apr 1998
Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English]01 Feb 1998
LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English]01 Jan 1998
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic small outline package; 14 leads; body width 3.9 mm (REV 1.0) PDF (166.0 kB) SOT108-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
SO14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... (REV 4.0) PDF (207.0 kB) SOT108-1_118 [English]08 Apr 2013
支持信息 (2)
名称/描述Modified Date
Footprint for reflow soldering (REV 1.0) PDF (9.0 kB) SO-SOJ-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (8.0 kB) SO-SOJ-WAVE [English]08 Oct 2009
IBIS
SPICE
订购信息
型号状态Family功能VCC (V)类型Logic switching levels说明Output drive capability (mA)Package versiontpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVT02DActiveLVTNOR gates2.7 - 3.6NOR gatesTTLquad 2-input NOR gate-32/+64SOT108-12.81504medium-40~8510820.367SO1414
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74LVT02DSOT108-1SO-SOJ-REFLOW SO-SOJ-WAVE
SO-SOJ-REFLOW SO-SOJ-WAVE
Reel 13" Q1/T1Active74LVT02D,118 (9352 089 50118)74LVT02D74LVT02Dweek 5, 200470.81.337.52E811
Bulk PackActive74LVT02D,112 (9352 089 50112)74LVT02D74LVT02Dweek 5, 200470.81.337.52E811
3.3 V Quad 2-input NOR gate 74LVT02PW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Test Fixtures for High Speed Logic 74ABTH162245ADL
Transmission Lines and Terminations with Philips Advanced Logic Families 74LVTN16245BDGG
LVT (Low Voltage Technology) and ALVT (Advanced LVT) 74LVTN16245BDGG
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
lvt02 IBIS model 74LVT02PW
lvt Spice model 74LVT640PW
plastic small outline package; 14 leads; body width 3.9 mm 74LV164_Q100
Footprint for reflow soldering NPIC6C596A_Q100
Footprint for wave soldering NPIC6C596A_Q100
SO14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... 74LV164_Q100
74LVT02
UBA2213